1*4882a593SmuzhiyunNVIDIA Tegra30 timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free 4*4882a593Smuzhiyunrunning counter, and 5 watchdog modules. The first two channels may also 5*4882a593Smuzhiyuntrigger a legacy watchdog reset. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, 10*4882a593Smuzhiyun must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where 11*4882a593Smuzhiyun <chip> is tegra124 or tegra132. 12*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers. 13*4882a593Smuzhiyun- interrupts : A list of 6 interrupts; one per each of timer channels 1 14*4882a593Smuzhiyun through 5, and one for the shared interrupt for the remaining channels. 15*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 16*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyuntimer { 19*4882a593Smuzhiyun compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 20*4882a593Smuzhiyun reg = <0x60005000 0x400>; 21*4882a593Smuzhiyun interrupts = <0 0 0x04 22*4882a593Smuzhiyun 0 1 0x04 23*4882a593Smuzhiyun 0 41 0x04 24*4882a593Smuzhiyun 0 42 0x04 25*4882a593Smuzhiyun 0 121 0x04 26*4882a593Smuzhiyun 0 122 0x04>; 27*4882a593Smuzhiyun clocks = <&tegra_car 214>; 28*4882a593Smuzhiyun}; 29