1*4882a593SmuzhiyunNVIDIA Tegra210 timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit 4*4882a593Smuzhiyuntimestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived 5*4882a593Smuzhiyunfrom the oscillator clock (TMR0-TMR9) or directly at the oscillator clock 6*4882a593Smuzhiyun(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, 7*4882a593Smuzhiyunor watchdog interrupts. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : "nvidia,tegra210-timer". 11*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers. 12*4882a593Smuzhiyun- interrupts : A list of 14 interrupts; one per each timer channels 0 through 13*4882a593Smuzhiyun 13. 14*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 15*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyuntimer@60005000 { 18*4882a593Smuzhiyun compatible = "nvidia,tegra210-timer"; 19*4882a593Smuzhiyun reg = <0x0 0x60005000 0x0 0x400>; 20*4882a593Smuzhiyun interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 21*4882a593Smuzhiyun <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 22*4882a593Smuzhiyun <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 23*4882a593Smuzhiyun <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 24*4882a593Smuzhiyun <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 25*4882a593Smuzhiyun <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 26*4882a593Smuzhiyun <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 27*4882a593Smuzhiyun <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 28*4882a593Smuzhiyun <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 29*4882a593Smuzhiyun <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 30*4882a593Smuzhiyun <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 31*4882a593Smuzhiyun <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 32*4882a593Smuzhiyun <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 33*4882a593Smuzhiyun <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 34*4882a593Smuzhiyun clocks = <&tegra_car TEGRA210_CLK_TIMER>; 35*4882a593Smuzhiyun clock-names = "timer"; 36*4882a593Smuzhiyun}; 37