1*4882a593SmuzhiyunNVIDIA Tegra20 timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Tegra20 timer provides four 29-bit timer channels and a single 32-bit free 4*4882a593Smuzhiyunrunning counter. The first two channels may also trigger a watchdog reset. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible : should be "nvidia,tegra20-timer". 9*4882a593Smuzhiyun- reg : Specifies base physical address and size of the registers. 10*4882a593Smuzhiyun- interrupts : A list of 4 interrupts; one per timer channel. 11*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 12*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyuntimer { 17*4882a593Smuzhiyun compatible = "nvidia,tegra20-timer"; 18*4882a593Smuzhiyun reg = <0x60005000 0x60>; 19*4882a593Smuzhiyun interrupts = <0 0 0x04 20*4882a593Smuzhiyun 0 1 0x04 21*4882a593Smuzhiyun 0 41 0x04 22*4882a593Smuzhiyun 0 42 0x04>; 23*4882a593Smuzhiyun clocks = <&tegra_car 132>; 24*4882a593Smuzhiyun}; 25