1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/mrvl,mmp-timer.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Marvell MMP Timer bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Daniel Lezcano <daniel.lezcano@linaro.org> 11*4882a593Smuzhiyun - Thomas Gleixner <tglx@linutronix.de> 12*4882a593Smuzhiyun - Rob Herring <robh+dt@kernel.org> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunproperties: 15*4882a593Smuzhiyun $nodename: 16*4882a593Smuzhiyun pattern: '^timer@[a-f0-9]+$' 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun const: mrvl,mmp-timer 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupts: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - compatible 32*4882a593Smuzhiyun - reg 33*4882a593Smuzhiyun - interrupts 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunadditionalProperties: false 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunexamples: 38*4882a593Smuzhiyun - | 39*4882a593Smuzhiyun timer@d4014000 { 40*4882a593Smuzhiyun compatible = "mrvl,mmp-timer"; 41*4882a593Smuzhiyun reg = <0xd4014000 0x100>; 42*4882a593Smuzhiyun interrupts = <13>; 43*4882a593Smuzhiyun clocks = <&coreclk 2>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun... 47