1*4882a593SmuzhiyunMediaTek Timers 2*4882a593Smuzhiyun--------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunMediaTek SoCs have two different timers on different platforms, 5*4882a593Smuzhiyun- GPT (General Purpose Timer) 6*4882a593Smuzhiyun- SYST (System Timer) 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunThe proper timer will be selected automatically by driver. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible should contain: 12*4882a593Smuzhiyun For those SoCs that use GPT 13*4882a593Smuzhiyun * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) 14*4882a593Smuzhiyun * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) 15*4882a593Smuzhiyun * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) 16*4882a593Smuzhiyun * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) 17*4882a593Smuzhiyun * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) 18*4882a593Smuzhiyun * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) 19*4882a593Smuzhiyun * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) 20*4882a593Smuzhiyun * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT) 21*4882a593Smuzhiyun * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun For those SoCs that use SYST 24*4882a593Smuzhiyun * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) 25*4882a593Smuzhiyun * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) 26*4882a593Smuzhiyun * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) 27*4882a593Smuzhiyun * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- reg: Should contain location and length for timer register. 30*4882a593Smuzhiyun- clocks: Should contain system clock. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExamples: 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun timer@10008000 { 35*4882a593Smuzhiyun compatible = "mediatek,mt6577-timer"; 36*4882a593Smuzhiyun reg = <0x10008000 0x80>; 37*4882a593Smuzhiyun interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; 38*4882a593Smuzhiyun clocks = <&system_clk>; 39*4882a593Smuzhiyun }; 40