1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2018 Linaro Ltd. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Intel IXP4xx XScale Networking Processors Timers 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Linus Walleij <linus.walleij@linaro.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: This timer is found in the Intel IXP4xx processors. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun items: 18*4882a593Smuzhiyun - const: intel,ixp4xx-timer 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun description: Should contain registers location and length 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupts: 24*4882a593Smuzhiyun minItems: 1 25*4882a593Smuzhiyun maxItems: 2 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: Timer 1 interrupt 28*4882a593Smuzhiyun - description: Timer 2 interrupt 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - compatible 32*4882a593Smuzhiyun - reg 33*4882a593Smuzhiyun - interrupts 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunadditionalProperties: false 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunexamples: 38*4882a593Smuzhiyun - | 39*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 40*4882a593Smuzhiyun timer@c8005000 { 41*4882a593Smuzhiyun compatible = "intel,ixp4xx-timer"; 42*4882a593Smuzhiyun reg = <0xc8005000 0x100>; 43*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 44*4882a593Smuzhiyun }; 45