1*4882a593Smuzhiyun* Freescale General-purpose Timers Module 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : should be 5*4882a593Smuzhiyun "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs 6*4882a593Smuzhiyun "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs 7*4882a593Smuzhiyun "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs 8*4882a593Smuzhiyun - reg : should contain gtm registers location and length (0x40). 9*4882a593Smuzhiyun - interrupts : should contain four interrupts. 10*4882a593Smuzhiyun - clock-frequency : specifies the frequency driving the timer. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunExample: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyuntimer@500 { 15*4882a593Smuzhiyun compatible = "fsl,mpc8360-gtm", "fsl,gtm"; 16*4882a593Smuzhiyun reg = <0x500 0x40>; 17*4882a593Smuzhiyun interrupts = <90 8 78 8 84 8 72 8>; 18*4882a593Smuzhiyun interrupt-parent = <&ipic>; 19*4882a593Smuzhiyun /* filled by u-boot */ 20*4882a593Smuzhiyun clock-frequency = <0>; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyuntimer@440 { 24*4882a593Smuzhiyun compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm"; 25*4882a593Smuzhiyun reg = <0x440 0x40>; 26*4882a593Smuzhiyun interrupts = <12 13 14 15>; 27*4882a593Smuzhiyun interrupt-parent = <&qeic>; 28*4882a593Smuzhiyun /* filled by u-boot */ 29*4882a593Smuzhiyun clock-frequency = <0>; 30*4882a593Smuzhiyun}; 31