1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Cadence TTC - Triple Timer Counter 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Michal Simek <michal.simek@xilinx.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun const: cdns,ttc 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg: 17*4882a593Smuzhiyun maxItems: 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun interrupts: 20*4882a593Smuzhiyun minItems: 3 21*4882a593Smuzhiyun maxItems: 3 22*4882a593Smuzhiyun description: | 23*4882a593Smuzhiyun A list of 3 interrupts; one per timer channel. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun timer-width: 29*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 30*4882a593Smuzhiyun description: | 31*4882a593Smuzhiyun Bit width of the timer, necessary if not 16. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunrequired: 34*4882a593Smuzhiyun - compatible 35*4882a593Smuzhiyun - reg 36*4882a593Smuzhiyun - interrupts 37*4882a593Smuzhiyun - clocks 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunadditionalProperties: false 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunexamples: 42*4882a593Smuzhiyun - | 43*4882a593Smuzhiyun ttc0: ttc0@f8001000 { 44*4882a593Smuzhiyun interrupt-parent = <&intc>; 45*4882a593Smuzhiyun interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 46*4882a593Smuzhiyun compatible = "cdns,ttc"; 47*4882a593Smuzhiyun reg = <0xF8001000 0x1000>; 48*4882a593Smuzhiyun clocks = <&cpu_clk 3>; 49*4882a593Smuzhiyun timer-width = <32>; 50*4882a593Smuzhiyun }; 51