xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: ARM memory mapped architected timer
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Marc Zyngier <marc.zyngier@arm.com>
11*4882a593Smuzhiyun  - Mark Rutland <mark.rutland@arm.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |+
14*4882a593Smuzhiyun  ARM cores may have a memory mapped architected timer, which provides up to 8
15*4882a593Smuzhiyun  frames with a physical and optional virtual timer per frame.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun  The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunproperties:
20*4882a593Smuzhiyun  compatible:
21*4882a593Smuzhiyun    items:
22*4882a593Smuzhiyun      - enum:
23*4882a593Smuzhiyun          - arm,armv7-timer-mem
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  reg:
26*4882a593Smuzhiyun    maxItems: 1
27*4882a593Smuzhiyun    description: The control frame base address
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  '#address-cells':
30*4882a593Smuzhiyun    enum: [1, 2]
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  '#size-cells':
33*4882a593Smuzhiyun    const: 1
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  ranges: true
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  clock-frequency:
38*4882a593Smuzhiyun    description: The frequency of the main counter, in Hz. Should be present
39*4882a593Smuzhiyun      only where necessary to work around broken firmware which does not configure
40*4882a593Smuzhiyun      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
41*4882a593Smuzhiyun      strongly discouraged; fix your firmware unless absolutely impossible.
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun  always-on:
44*4882a593Smuzhiyun    type: boolean
45*4882a593Smuzhiyun    description: If present, the timer is powered through an always-on power
46*4882a593Smuzhiyun      domain, therefore it never loses context.
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun  arm,cpu-registers-not-fw-configured:
49*4882a593Smuzhiyun    type: boolean
50*4882a593Smuzhiyun    description: Firmware does not initialize any of the generic timer CPU
51*4882a593Smuzhiyun      registers, which contain their architecturally-defined reset values. Only
52*4882a593Smuzhiyun      supported for 32-bit systems which follow the ARMv7 architected reset
53*4882a593Smuzhiyun      values.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun  arm,no-tick-in-suspend:
56*4882a593Smuzhiyun    type: boolean
57*4882a593Smuzhiyun    description: The main counter does not tick when the system is in
58*4882a593Smuzhiyun      low-power system suspend on some SoCs. This behavior does not match the
59*4882a593Smuzhiyun      Architecture Reference Manual's specification that the system counter "must
60*4882a593Smuzhiyun      be implemented in an always-on power domain."
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunpatternProperties:
63*4882a593Smuzhiyun  '^frame@[0-9a-z]*$':
64*4882a593Smuzhiyun    type: object
65*4882a593Smuzhiyun    description: A timer node has up to 8 frame sub-nodes, each with the following properties.
66*4882a593Smuzhiyun    properties:
67*4882a593Smuzhiyun      frame-number:
68*4882a593Smuzhiyun        $ref: "/schemas/types.yaml#/definitions/uint32"
69*4882a593Smuzhiyun        minimum: 0
70*4882a593Smuzhiyun        maximum: 7
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun      interrupts:
73*4882a593Smuzhiyun        minItems: 1
74*4882a593Smuzhiyun        maxItems: 2
75*4882a593Smuzhiyun        items:
76*4882a593Smuzhiyun          - description: physical timer irq
77*4882a593Smuzhiyun          - description: virtual timer irq
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun      reg:
80*4882a593Smuzhiyun        minItems: 1
81*4882a593Smuzhiyun        maxItems: 2
82*4882a593Smuzhiyun        items:
83*4882a593Smuzhiyun          - description: 1st view base address
84*4882a593Smuzhiyun          - description: 2nd optional view base address
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun    required:
87*4882a593Smuzhiyun      - frame-number
88*4882a593Smuzhiyun      - interrupts
89*4882a593Smuzhiyun      - reg
90*4882a593Smuzhiyun
91*4882a593Smuzhiyunrequired:
92*4882a593Smuzhiyun  - compatible
93*4882a593Smuzhiyun  - reg
94*4882a593Smuzhiyun  - '#address-cells'
95*4882a593Smuzhiyun  - '#size-cells'
96*4882a593Smuzhiyun
97*4882a593SmuzhiyunadditionalProperties: false
98*4882a593Smuzhiyun
99*4882a593Smuzhiyunexamples:
100*4882a593Smuzhiyun  - |
101*4882a593Smuzhiyun    timer@f0000000 {
102*4882a593Smuzhiyun      compatible = "arm,armv7-timer-mem";
103*4882a593Smuzhiyun      #address-cells = <1>;
104*4882a593Smuzhiyun      #size-cells = <1>;
105*4882a593Smuzhiyun      ranges = <0 0xf0001000 0x1000>;
106*4882a593Smuzhiyun      reg = <0xf0000000 0x1000>;
107*4882a593Smuzhiyun      clock-frequency = <50000000>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun      frame@0 {
110*4882a593Smuzhiyun        frame-number = <0>;
111*4882a593Smuzhiyun        interrupts = <0 13 0x8>,
112*4882a593Smuzhiyun               <0 14 0x8>;
113*4882a593Smuzhiyun        reg = <0x0000 0x1000>,
114*4882a593Smuzhiyun              <0x1000 0x1000>;
115*4882a593Smuzhiyun      };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun      frame@2000 {
118*4882a593Smuzhiyun        frame-number = <1>;
119*4882a593Smuzhiyun        interrupts = <0 15 0x8>;
120*4882a593Smuzhiyun        reg = <0x2000 0x1000>;
121*4882a593Smuzhiyun      };
122*4882a593Smuzhiyun    };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun...
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