1*4882a593SmuzhiyunAndestech ATCPIT100 timer 2*4882a593Smuzhiyun------------------------------------------------------------------ 3*4882a593SmuzhiyunATCPIT100 is a generic IP block from Andes Technology, embedded in 4*4882a593SmuzhiyunAndestech AE3XX platforms and other designs. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis timer is a set of compact multi-function timers, which can be 7*4882a593Smuzhiyunused as pulse width modulators (PWM) as well as simple timers. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunIt supports up to 4 PIT channels. Each PIT channel is a 10*4882a593Smuzhiyunmulti-function timer and provide the following usage scenarios: 11*4882a593SmuzhiyunOne 32-bit timer 12*4882a593SmuzhiyunTwo 16-bit timers 13*4882a593SmuzhiyunFour 8-bit timers 14*4882a593SmuzhiyunOne 16-bit PWM 15*4882a593SmuzhiyunOne 16-bit timer and one 8-bit PWM 16*4882a593SmuzhiyunTwo 8-bit timer and one 8-bit PWM 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun- compatible : Should be "andestech,atcpit100" 20*4882a593Smuzhiyun- reg : Address and length of the register set 21*4882a593Smuzhiyun- interrupts : Reference to the timer interrupt 22*4882a593Smuzhiyun- clocks : a clock to provide the tick rate for "andestech,atcpit100" 23*4882a593Smuzhiyun- clock-names : should be "PCLK" for the peripheral clock source. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExamples: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyuntimer0: timer@f0400000 { 28*4882a593Smuzhiyun compatible = "andestech,atcpit100"; 29*4882a593Smuzhiyun reg = <0xf0400000 0x1000>; 30*4882a593Smuzhiyun interrupts = <2>; 31*4882a593Smuzhiyun clocks = <&apb>; 32*4882a593Smuzhiyun clock-names = "PCLK"; 33*4882a593Smuzhiyun}; 34