1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun# Copyright 2019 Linaro Ltd. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: QCOM SoC Temperature Sensor (TSENS) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Amit Kucheria <amitk@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15*4882a593Smuzhiyun three distinct major versions of the IP that is supported by a single driver. 16*4882a593Smuzhiyun The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17*4882a593Smuzhiyun everything before v1 when there was no versioning information. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun oneOf: 22*4882a593Smuzhiyun - description: v0.1 of TSENS 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - enum: 25*4882a593Smuzhiyun - qcom,msm8916-tsens 26*4882a593Smuzhiyun - qcom,msm8939-tsens 27*4882a593Smuzhiyun - qcom,msm8974-tsens 28*4882a593Smuzhiyun - const: qcom,tsens-v0_1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun - description: v1 of TSENS 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - enum: 33*4882a593Smuzhiyun - qcom,msm8976-tsens 34*4882a593Smuzhiyun - qcom,qcs404-tsens 35*4882a593Smuzhiyun - const: qcom,tsens-v1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun - description: v2 of TSENS 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun - enum: 40*4882a593Smuzhiyun - qcom,msm8996-tsens 41*4882a593Smuzhiyun - qcom,msm8998-tsens 42*4882a593Smuzhiyun - qcom,sc7180-tsens 43*4882a593Smuzhiyun - qcom,sdm845-tsens 44*4882a593Smuzhiyun - qcom,sm8150-tsens 45*4882a593Smuzhiyun - qcom,sm8250-tsens 46*4882a593Smuzhiyun - const: qcom,tsens-v2 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun reg: 49*4882a593Smuzhiyun items: 50*4882a593Smuzhiyun - description: TM registers 51*4882a593Smuzhiyun - description: SROT registers 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun interrupts: 54*4882a593Smuzhiyun minItems: 1 55*4882a593Smuzhiyun items: 56*4882a593Smuzhiyun - description: Combined interrupt if upper or lower threshold crossed 57*4882a593Smuzhiyun - description: Interrupt if critical threshold crossed 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun interrupt-names: 60*4882a593Smuzhiyun minItems: 1 61*4882a593Smuzhiyun items: 62*4882a593Smuzhiyun - const: uplow 63*4882a593Smuzhiyun - const: critical 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun nvmem-cells: 66*4882a593Smuzhiyun minItems: 1 67*4882a593Smuzhiyun maxItems: 2 68*4882a593Smuzhiyun description: 69*4882a593Smuzhiyun Reference to an nvmem node for the calibration data 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun nvmem-cell-names: 72*4882a593Smuzhiyun minItems: 1 73*4882a593Smuzhiyun maxItems: 2 74*4882a593Smuzhiyun items: 75*4882a593Smuzhiyun - const: calib 76*4882a593Smuzhiyun - const: calib_sel 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun "#qcom,sensors": 79*4882a593Smuzhiyun description: 80*4882a593Smuzhiyun Number of sensors enabled on this platform 81*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 82*4882a593Smuzhiyun minimum: 1 83*4882a593Smuzhiyun maximum: 16 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun "#thermal-sensor-cells": 86*4882a593Smuzhiyun const: 1 87*4882a593Smuzhiyun description: 88*4882a593Smuzhiyun Number of cells required to uniquely identify the thermal sensors. Since 89*4882a593Smuzhiyun we have multiple sensors this is set to 1 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunallOf: 92*4882a593Smuzhiyun - if: 93*4882a593Smuzhiyun properties: 94*4882a593Smuzhiyun compatible: 95*4882a593Smuzhiyun contains: 96*4882a593Smuzhiyun enum: 97*4882a593Smuzhiyun - qcom,msm8916-tsens 98*4882a593Smuzhiyun - qcom,msm8974-tsens 99*4882a593Smuzhiyun - qcom,msm8976-tsens 100*4882a593Smuzhiyun - qcom,qcs404-tsens 101*4882a593Smuzhiyun - qcom,tsens-v0_1 102*4882a593Smuzhiyun - qcom,tsens-v1 103*4882a593Smuzhiyun then: 104*4882a593Smuzhiyun properties: 105*4882a593Smuzhiyun interrupts: 106*4882a593Smuzhiyun maxItems: 1 107*4882a593Smuzhiyun interrupt-names: 108*4882a593Smuzhiyun maxItems: 1 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun else: 111*4882a593Smuzhiyun properties: 112*4882a593Smuzhiyun interrupts: 113*4882a593Smuzhiyun minItems: 2 114*4882a593Smuzhiyun interrupt-names: 115*4882a593Smuzhiyun minItems: 2 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunrequired: 118*4882a593Smuzhiyun - compatible 119*4882a593Smuzhiyun - reg 120*4882a593Smuzhiyun - "#qcom,sensors" 121*4882a593Smuzhiyun - interrupts 122*4882a593Smuzhiyun - interrupt-names 123*4882a593Smuzhiyun - "#thermal-sensor-cells" 124*4882a593Smuzhiyun 125*4882a593SmuzhiyunadditionalProperties: false 126*4882a593Smuzhiyun 127*4882a593Smuzhiyunexamples: 128*4882a593Smuzhiyun - | 129*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 130*4882a593Smuzhiyun // Example 1 (legacy: for pre v1 IP): 131*4882a593Smuzhiyun tsens1: thermal-sensor@900000 { 132*4882a593Smuzhiyun compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 133*4882a593Smuzhiyun reg = <0x4a9000 0x1000>, /* TM */ 134*4882a593Smuzhiyun <0x4a8000 0x1000>; /* SROT */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 137*4882a593Smuzhiyun nvmem-cell-names = "calib", "calib_sel"; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 140*4882a593Smuzhiyun interrupt-names = "uplow"; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #qcom,sensors = <5>; 143*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun - | 147*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 148*4882a593Smuzhiyun // Example 2 (for any platform containing v1 of the TSENS IP): 149*4882a593Smuzhiyun tsens2: thermal-sensor@4a9000 { 150*4882a593Smuzhiyun compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 151*4882a593Smuzhiyun reg = <0x004a9000 0x1000>, /* TM */ 152*4882a593Smuzhiyun <0x004a8000 0x1000>; /* SROT */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun nvmem-cells = <&tsens_caldata>; 155*4882a593Smuzhiyun nvmem-cell-names = "calib"; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 158*4882a593Smuzhiyun interrupt-names = "uplow"; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #qcom,sensors = <10>; 161*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun - | 165*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 166*4882a593Smuzhiyun // Example 3 (for any platform containing v2 of the TSENS IP): 167*4882a593Smuzhiyun tsens3: thermal-sensor@c263000 { 168*4882a593Smuzhiyun compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 169*4882a593Smuzhiyun reg = <0xc263000 0x1ff>, 170*4882a593Smuzhiyun <0xc222000 0x1ff>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 173*4882a593Smuzhiyun <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 174*4882a593Smuzhiyun interrupt-names = "uplow", "critical"; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #qcom,sensors = <13>; 177*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun... 180