1*4882a593SmuzhiyunTegra124 SOCTHERM thermal management system 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe SOCTHERM IP block contains thermal sensors, support for polled 4*4882a593Smuzhiyunor interrupt-based thermal monitoring, CPU and GPU throttling based 5*4882a593Smuzhiyunon temperature trip points, and handling external overcurrent 6*4882a593Smuzhiyunnotifications. It is also used to manage emergency shutdown in an 7*4882a593Smuzhiyunoverheating situation. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties : 10*4882a593Smuzhiyun- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". 11*4882a593Smuzhiyun For Tegra132, must contain "nvidia,tegra132-soctherm". 12*4882a593Smuzhiyun For Tegra210, must contain "nvidia,tegra210-soctherm". 13*4882a593Smuzhiyun- reg : Should contain at least 2 entries for each entry in reg-names: 14*4882a593Smuzhiyun - SOCTHERM register set 15*4882a593Smuzhiyun - Tegra CAR register set: Required for Tegra124 and Tegra210. 16*4882a593Smuzhiyun - CCROC register set: Required for Tegra132. 17*4882a593Smuzhiyun- reg-names : Should contain at least 2 entries: 18*4882a593Smuzhiyun - soctherm-reg 19*4882a593Smuzhiyun - car-reg 20*4882a593Smuzhiyun - ccroc-reg 21*4882a593Smuzhiyun- interrupts : Defines the interrupt used by SOCTHERM 22*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 23*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 24*4882a593Smuzhiyun- clock-names : Must include the following entries: 25*4882a593Smuzhiyun - tsensor 26*4882a593Smuzhiyun - soctherm 27*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 28*4882a593Smuzhiyun See ../reset/reset.txt for details. 29*4882a593Smuzhiyun- reset-names : Must include the following entries: 30*4882a593Smuzhiyun - soctherm 31*4882a593Smuzhiyun- #thermal-sensor-cells : Should be 1. For a description of this property, see 32*4882a593Smuzhiyun Documentation/devicetree/bindings/thermal/thermal-sensor.yaml. 33*4882a593Smuzhiyun See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values 34*4882a593Smuzhiyun when referring to thermal sensors. 35*4882a593Smuzhiyun- throttle-cfgs: A sub-node which is a container of configuration for each 36*4882a593Smuzhiyun hardware throttle events. These events can be set as cooling devices. 37*4882a593Smuzhiyun * throttle events: Sub-nodes must be named as "light" or "heavy". 38*4882a593Smuzhiyun Properties: 39*4882a593Smuzhiyun - nvidia,priority: Each throttles has its own throttle settings, so the 40*4882a593Smuzhiyun SW need to set priorities for various throttle, the HW arbiter can select 41*4882a593Smuzhiyun the final throttle settings. 42*4882a593Smuzhiyun Bigger value indicates higher priority, In general, higher priority 43*4882a593Smuzhiyun translates to lower target frequency. SW needs to ensure that critical 44*4882a593Smuzhiyun thermal alarms are given higher priority, and ensure that there is 45*4882a593Smuzhiyun no race if priority of two vectors is set to the same value. 46*4882a593Smuzhiyun The range of this value is 1~100. 47*4882a593Smuzhiyun - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210. 48*4882a593Smuzhiyun It is the throttling depth of pulse skippers, it's the percentage 49*4882a593Smuzhiyun throttling. 50*4882a593Smuzhiyun - nvidia,cpu-throt-level: This property is only for Tegra132, it is the 51*4882a593Smuzhiyun level of pulse skippers, which used to throttle clock frequencies. It 52*4882a593Smuzhiyun indicates cpu clock throttling depth, and the depth can be programmed. 53*4882a593Smuzhiyun Must set as following values: 54*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED 55*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE 56*4882a593Smuzhiyun - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210. 57*4882a593Smuzhiyun It is the level of pulse skippers, which used to throttle clock 58*4882a593Smuzhiyun frequencies. It indicates gpu clock throttling depth and can be 59*4882a593Smuzhiyun programmed to any of the following values which represent a throttling 60*4882a593Smuzhiyun percentage: 61*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%) 62*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%), 63*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_MED (75%), 64*4882a593Smuzhiyun TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%). 65*4882a593Smuzhiyun - #cooling-cells: Should be 1. This cooling device only support on/off state. 66*4882a593Smuzhiyun For a description of this property see: 67*4882a593Smuzhiyun Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun Optional properties: The following properties are T210 specific and 70*4882a593Smuzhiyun valid only for OCx throttle events. 71*4882a593Smuzhiyun - nvidia,count-threshold: Specifies the number of OC events that are 72*4882a593Smuzhiyun required for triggering an interrupt. Interrupts are not triggered if 73*4882a593Smuzhiyun the property is missing. A value of 0 will interrupt on every OC alarm. 74*4882a593Smuzhiyun - nvidia,polarity-active-low: Configures the polarity of the OC alaram 75*4882a593Smuzhiyun signal. If present, this means assert low, otherwise assert high. 76*4882a593Smuzhiyun - nvidia,alarm-filter: Number of clocks to filter event. When the filter 77*4882a593Smuzhiyun expires (which means the OC event has not occurred for a long time), 78*4882a593Smuzhiyun the counter is cleared and filter is rearmed. Default value is 0. 79*4882a593Smuzhiyun - nvidia,throttle-period-us: Specifies the number of uSec for which 80*4882a593Smuzhiyun throttling is engaged after the OC event is deasserted. Default value 81*4882a593Smuzhiyun is 0. 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunOptional properties: 84*4882a593Smuzhiyun- nvidia,thermtrips : When present, this property specifies the temperature at 85*4882a593Smuzhiyun which the soctherm hardware will assert the thermal trigger signal to the 86*4882a593Smuzhiyun Power Management IC, which can be configured to reset or shutdown the device. 87*4882a593Smuzhiyun It is an array of pairs where each pair represents a tsensor id followed by a 88*4882a593Smuzhiyun temperature in milli Celcius. In the absence of this property the critical 89*4882a593Smuzhiyun trip point will be used for thermtrip temperature. 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunNote: 92*4882a593Smuzhiyun- the "critical" type trip points will be used to set the temperature at which 93*4882a593Smuzhiyunthe SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips" 94*4882a593Smuzhiyunproperty is missing. When the thermtrips property is present, the breach of a 95*4882a593Smuzhiyuncritical trip point is reported back to the thermal framework to implement 96*4882a593Smuzhiyunsoftware shutdown. 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun- the "hot" type trip points will be set to SOC_THERM hardware as the throttle 99*4882a593Smuzhiyuntemperature. Once the the temperature of this thermal zone is higher 100*4882a593Smuzhiyunthan it, it will trigger the HW throttle event. 101*4882a593Smuzhiyun 102*4882a593SmuzhiyunExample : 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun soctherm@700e2000 { 105*4882a593Smuzhiyun compatible = "nvidia,tegra124-soctherm"; 106*4882a593Smuzhiyun reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 107*4882a593Smuzhiyun 0x0 0x60006000 0x0 0x400 /* CAR reg_base */ 108*4882a593Smuzhiyun reg-names = "soctherm-reg", "car-reg"; 109*4882a593Smuzhiyun interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 110*4882a593Smuzhiyun clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 111*4882a593Smuzhiyun <&tegra_car TEGRA124_CLK_SOC_THERM>; 112*4882a593Smuzhiyun clock-names = "tsensor", "soctherm"; 113*4882a593Smuzhiyun resets = <&tegra_car 78>; 114*4882a593Smuzhiyun reset-names = "soctherm"; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500 119*4882a593Smuzhiyun TEGRA124_SOCTHERM_SENSOR_GPU 103000>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun throttle-cfgs { 122*4882a593Smuzhiyun /* 123*4882a593Smuzhiyun * When the "heavy" cooling device triggered, 124*4882a593Smuzhiyun * the HW will skip cpu clock's pulse in 85% depth, 125*4882a593Smuzhiyun * skip gpu clock's pulse in 85% level 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun throttle_heavy: heavy { 128*4882a593Smuzhiyun nvidia,priority = <100>; 129*4882a593Smuzhiyun nvidia,cpu-throt-percent = <85>; 130*4882a593Smuzhiyun nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #cooling-cells = <1>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* 136*4882a593Smuzhiyun * When the "light" cooling device triggered, 137*4882a593Smuzhiyun * the HW will skip cpu clock's pulse in 50% depth, 138*4882a593Smuzhiyun * skip gpu clock's pulse in 50% level 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun throttle_light: light { 141*4882a593Smuzhiyun nvidia,priority = <80>; 142*4882a593Smuzhiyun nvidia,cpu-throt-percent = <50>; 143*4882a593Smuzhiyun nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #cooling-cells = <1>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * If these two devices are triggered in same time, the HW throttle 150*4882a593Smuzhiyun * arbiter will select the highest priority as the final throttle 151*4882a593Smuzhiyun * settings to skip cpu pulse. 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun throttle_oc1: oc1 { 155*4882a593Smuzhiyun nvidia,priority = <50>; 156*4882a593Smuzhiyun nvidia,polarity-active-low; 157*4882a593Smuzhiyun nvidia,count-threshold = <100>; 158*4882a593Smuzhiyun nvidia,alarm-filter = <5100000>; 159*4882a593Smuzhiyun nvidia,throttle-period-us = <0>; 160*4882a593Smuzhiyun nvidia,cpu-throt-percent = <75>; 161*4882a593Smuzhiyun nvidia,gpu-throt-level = 162*4882a593Smuzhiyun <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593SmuzhiyunExample: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" : 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun soctherm@700e2000 { 170*4882a593Smuzhiyun compatible = "nvidia,tegra132-soctherm"; 171*4882a593Smuzhiyun reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 172*4882a593Smuzhiyun 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */; 173*4882a593Smuzhiyun reg-names = "soctherm-reg", "ccroc-reg"; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun throttle-cfgs { 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * When the "heavy" cooling device triggered, 178*4882a593Smuzhiyun * the HW will skip cpu clock's pulse in HIGH level 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun throttle_heavy: heavy { 181*4882a593Smuzhiyun nvidia,priority = <100>; 182*4882a593Smuzhiyun nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #cooling-cells = <1>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* 188*4882a593Smuzhiyun * When the "light" cooling device triggered, 189*4882a593Smuzhiyun * the HW will skip cpu clock's pulse in MED level 190*4882a593Smuzhiyun */ 191*4882a593Smuzhiyun throttle_light: light { 192*4882a593Smuzhiyun nvidia,priority = <80>; 193*4882a593Smuzhiyun nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #cooling-cells = <1>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* 199*4882a593Smuzhiyun * If these two devices are triggered in same time, the HW throttle 200*4882a593Smuzhiyun * arbiter will select the highest priority as the final throttle 201*4882a593Smuzhiyun * settings to skip cpu pulse. 202*4882a593Smuzhiyun */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593SmuzhiyunExample: referring to thermal sensors : 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun thermal-zones { 210*4882a593Smuzhiyun cpu { 211*4882a593Smuzhiyun polling-delay-passive = <1000>; 212*4882a593Smuzhiyun polling-delay = <1000>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun thermal-sensors = 215*4882a593Smuzhiyun <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun trips { 218*4882a593Smuzhiyun cpu_shutdown_trip: shutdown-trip { 219*4882a593Smuzhiyun temperature = <102500>; 220*4882a593Smuzhiyun hysteresis = <1000>; 221*4882a593Smuzhiyun type = "critical"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun cpu_throttle_trip: throttle-trip { 225*4882a593Smuzhiyun temperature = <100000>; 226*4882a593Smuzhiyun hysteresis = <1000>; 227*4882a593Smuzhiyun type = "hot"; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun cooling-maps { 232*4882a593Smuzhiyun map0 { 233*4882a593Smuzhiyun trip = <&cpu_throttle_trip>; 234*4882a593Smuzhiyun cooling-device = <&throttle_heavy 1 1>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239