1*4882a593Smuzhiyun* Mediatek Thermal 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis describes the device tree binding for the Mediatek thermal controller 4*4882a593Smuzhiyunwhich measures the on-SoC temperatures. This device does not have its own ADC, 5*4882a593Smuzhiyuninstead it directly controls the AUXADC via AHB bus accesses. For this reason 6*4882a593Smuzhiyunthis device needs phandles to the AUXADC. Also it controls a mux in the 7*4882a593Smuzhiyunapmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS 8*4882a593Smuzhiyunis also needed. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: 12*4882a593Smuzhiyun - "mediatek,mt8173-thermal" : For MT8173 family of SoCs 13*4882a593Smuzhiyun - "mediatek,mt2701-thermal" : For MT2701 family of SoCs 14*4882a593Smuzhiyun - "mediatek,mt2712-thermal" : For MT2712 family of SoCs 15*4882a593Smuzhiyun - "mediatek,mt7622-thermal" : For MT7622 SoC 16*4882a593Smuzhiyun - "mediatek,mt8183-thermal" : For MT8183 family of SoCs 17*4882a593Smuzhiyun- reg: Address range of the thermal controller 18*4882a593Smuzhiyun- interrupts: IRQ for the thermal controller 19*4882a593Smuzhiyun- clocks, clock-names: Clocks needed for the thermal controller. required 20*4882a593Smuzhiyun clocks are: 21*4882a593Smuzhiyun "therm": Main clock needed for register access 22*4882a593Smuzhiyun "auxadc": The AUXADC clock 23*4882a593Smuzhiyun- resets: Reference to the reset controller controlling the thermal controller. 24*4882a593Smuzhiyun- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses 25*4882a593Smuzhiyun- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. 26*4882a593Smuzhiyun- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunOptional properties: 29*4882a593Smuzhiyun- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If 30*4882a593Smuzhiyun unspecified default values shall be used. 31*4882a593Smuzhiyun- nvmem-cell-names: Should be "calibration-data" 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun thermal: thermal@1100b000 { 36*4882a593Smuzhiyun #thermal-sensor-cells = <1>; 37*4882a593Smuzhiyun compatible = "mediatek,mt8173-thermal"; 38*4882a593Smuzhiyun reg = <0 0x1100b000 0 0x1000>; 39*4882a593Smuzhiyun interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 40*4882a593Smuzhiyun clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 41*4882a593Smuzhiyun clock-names = "therm", "auxadc"; 42*4882a593Smuzhiyun resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 43*4882a593Smuzhiyun reset-names = "therm"; 44*4882a593Smuzhiyun mediatek,auxadc = <&auxadc>; 45*4882a593Smuzhiyun mediatek,apmixedsys = <&apmixedsys>; 46*4882a593Smuzhiyun nvmem-cells = <&thermal_calibration_data>; 47*4882a593Smuzhiyun nvmem-cell-names = "calibration-data"; 48*4882a593Smuzhiyun }; 49