1*4882a593Smuzhiyun* Marvell Armada 370/375/380/XP thermal management 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: Should be set to one of the following: 6*4882a593Smuzhiyun * marvell,armada370-thermal 7*4882a593Smuzhiyun * marvell,armada375-thermal 8*4882a593Smuzhiyun * marvell,armada380-thermal 9*4882a593Smuzhiyun * marvell,armadaxp-thermal 10*4882a593Smuzhiyun * marvell,armada-ap806-thermal 11*4882a593Smuzhiyun * marvell,armada-cp110-thermal 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunNote: these bindings are deprecated for AP806/CP110 and should instead 14*4882a593Smuzhiyunfollow the rules described in: 15*4882a593SmuzhiyunDocumentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt 16*4882a593SmuzhiyunDocumentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- reg: Device's register space. 19*4882a593Smuzhiyun Two entries are expected, see the examples below. The first one points 20*4882a593Smuzhiyun to the status register (4B). The second one points to the control 21*4882a593Smuzhiyun registers (8B). 22*4882a593Smuzhiyun Note: The compatibles marvell,armada370-thermal, 23*4882a593Smuzhiyun marvell,armada380-thermal, and marvell,armadaxp-thermal must point to 24*4882a593Smuzhiyun "control MSB/control 1", with size of 4 (deprecated binding), or point 25*4882a593Smuzhiyun to "control LSB/control 0" with size of 8 (current binding). All other 26*4882a593Smuzhiyun compatibles must point to "control LSB/control 0" with size of 8. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExamples: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Legacy bindings */ 31*4882a593Smuzhiyun thermal@d0018300 { 32*4882a593Smuzhiyun compatible = "marvell,armada370-thermal"; 33*4882a593Smuzhiyun reg = <0xd0018300 0x4 34*4882a593Smuzhiyun 0xd0018304 0x4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ap_thermal: thermal@6f8084 { 38*4882a593Smuzhiyun compatible = "marvell,armada-ap806-thermal"; 39*4882a593Smuzhiyun reg = <0x6f808C 0x4>, 40*4882a593Smuzhiyun <0x6f8084 0x8>; 41*4882a593Smuzhiyun }; 42