1*4882a593SmuzhiyunQualcomm SPMI Controller (PMIC Arbiter) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI 4*4882a593Smuzhiyuncontroller with wrapping arbitration logic to allow for multiple on-chip 5*4882a593Smuzhiyundevices to control a single SPMI master. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe PMIC Arbiter can also act as an interrupt controller, providing interrupts 8*4882a593Smuzhiyunto slave devices. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunSee Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI 11*4882a593Smuzhiyuncontroller binding requirements for child nodes. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunSee Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for 14*4882a593Smuzhiyungeneric interrupt controller binding documentation. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun- compatible : should be "qcom,spmi-pmic-arb". 18*4882a593Smuzhiyun- reg-names : must contain: 19*4882a593Smuzhiyun "core" - core registers 20*4882a593Smuzhiyun "intr" - interrupt controller registers 21*4882a593Smuzhiyun "cnfg" - configuration registers 22*4882a593Smuzhiyun Registers used only for V2 PMIC Arbiter: 23*4882a593Smuzhiyun "chnls" - tx-channel per virtual slave registers. 24*4882a593Smuzhiyun "obsrvr" - rx-channel (called observer) per virtual slave registers. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- reg : address + size pairs describing the PMIC arb register sets; order must 27*4882a593Smuzhiyun correspond with the order of entries in reg-names 28*4882a593Smuzhiyun- #address-cells : must be set to 2 29*4882a593Smuzhiyun- #size-cells : must be set to 0 30*4882a593Smuzhiyun- qcom,ee : indicates the active Execution Environment identifier (0-5) 31*4882a593Smuzhiyun- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) 32*4882a593Smuzhiyun- interrupts : interrupt list for the PMIC Arb controller, must contain a 33*4882a593Smuzhiyun single interrupt entry for the peripheral interrupt 34*4882a593Smuzhiyun- interrupt-names : corresponding interrupt names for the interrupts 35*4882a593Smuzhiyun listed in the 'interrupts' property, must contain: 36*4882a593Smuzhiyun "periph_irq" - summary interrupt for PMIC peripherals 37*4882a593Smuzhiyun- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller 38*4882a593Smuzhiyun- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: 39*4882a593Smuzhiyun cell 1: slave ID for the requested interrupt (0-15) 40*4882a593Smuzhiyun cell 2: peripheral ID for requested interrupt (0-255) 41*4882a593Smuzhiyun cell 3: the requested peripheral interrupt (0-7) 42*4882a593Smuzhiyun cell 4: interrupt flags indicating level-sense information, as defined in 43*4882a593Smuzhiyun dt-bindings/interrupt-controller/irq.h 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExample: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun spmi { 48*4882a593Smuzhiyun compatible = "qcom,spmi-pmic-arb"; 49*4882a593Smuzhiyun reg-names = "core", "intr", "cnfg"; 50*4882a593Smuzhiyun reg = <0xfc4cf000 0x1000>, 51*4882a593Smuzhiyun <0xfc4cb000 0x1000>, 52*4882a593Smuzhiyun <0xfc4ca000 0x1000>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun interrupt-names = "periph_irq"; 55*4882a593Smuzhiyun interrupts = <0 190 0>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun qcom,ee = <0>; 58*4882a593Smuzhiyun qcom,channel = <0>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #address-cells = <2>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun #interrupt-cells = <4>; 65*4882a593Smuzhiyun }; 66