1*4882a593SmuzhiyunAtmel SPI device 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi". 5*4882a593Smuzhiyun- reg: Address and length of the register set for the device 6*4882a593Smuzhiyun- interrupts: Should contain spi interrupt 7*4882a593Smuzhiyun- cs-gpios: chipselects (optional for SPI controller version >= 2 with the 8*4882a593Smuzhiyun Chip Select Active After Transfer feature). 9*4882a593Smuzhiyun- clock-names: tuple listing input clock names. 10*4882a593Smuzhiyun Required elements: "spi_clk" 11*4882a593Smuzhiyun- clocks: phandles to input clocks. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties: 14*4882a593Smuzhiyun- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO 15*4882a593Smuzhiyun capable SPI controllers. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunspi1: spi@fffcc000 { 20*4882a593Smuzhiyun compatible = "atmel,at91rm9200-spi"; 21*4882a593Smuzhiyun reg = <0xfffcc000 0x4000>; 22*4882a593Smuzhiyun interrupts = <13 4 5>; 23*4882a593Smuzhiyun #address-cells = <1>; 24*4882a593Smuzhiyun #size-cells = <0>; 25*4882a593Smuzhiyun clocks = <&spi1_clk>; 26*4882a593Smuzhiyun clock-names = "spi_clk"; 27*4882a593Smuzhiyun cs-gpios = <&pioB 3 0>; 28*4882a593Smuzhiyun atmel,fifo-size = <32>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun mmc-slot@0 { 31*4882a593Smuzhiyun compatible = "mmc-spi-slot"; 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun gpios = <&pioC 4 0>; /* CD */ 34*4882a593Smuzhiyun spi-max-frequency = <25000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37