1*4882a593SmuzhiyunXilinx Zynq QSPI controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Should be "xlnx,zynq-qspi-1.0". 6*4882a593Smuzhiyun- reg : Physical base address and size of QSPI registers map. 7*4882a593Smuzhiyun- interrupts : Property with a value describing the interrupt 8*4882a593Smuzhiyun number. 9*4882a593Smuzhiyun- clock-names : List of input clock names - "ref_clk", "pclk" 10*4882a593Smuzhiyun (See clock bindings for details). 11*4882a593Smuzhiyun- clocks : Clock phandles (see clock bindings for details). 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties: 14*4882a593Smuzhiyun- num-cs : Number of chip selects used. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun qspi: spi@e000d000 { 18*4882a593Smuzhiyun compatible = "xlnx,zynq-qspi-1.0"; 19*4882a593Smuzhiyun reg = <0xe000d000 0x1000>; 20*4882a593Smuzhiyun interrupt-parent = <&intc>; 21*4882a593Smuzhiyun interrupts = <0 19 4>; 22*4882a593Smuzhiyun clock-names = "ref_clk", "pclk"; 23*4882a593Smuzhiyun clocks = <&clkc 10>, <&clkc 43>; 24*4882a593Smuzhiyun num-cs = <1>; 25*4882a593Smuzhiyun }; 26