1*4882a593SmuzhiyunXilinx SPI controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Should be "xlnx,xps-spi-2.00.a", "xlnx,xps-spi-2.00.b" or "xlnx,axi-quad-spi-1.00.a" 6*4882a593Smuzhiyun- reg : Physical base address and size of SPI registers map. 7*4882a593Smuzhiyun- interrupts : Property with a value describing the interrupt 8*4882a593Smuzhiyun number. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties: 11*4882a593Smuzhiyun- xlnx,num-ss-bits : Number of chip selects used. 12*4882a593Smuzhiyun- xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun axi_quad_spi@41e00000 { 16*4882a593Smuzhiyun compatible = "xlnx,xps-spi-2.00.a"; 17*4882a593Smuzhiyun interrupt-parent = <&intc>; 18*4882a593Smuzhiyun interrupts = <0 31 1>; 19*4882a593Smuzhiyun reg = <0x41e00000 0x10000>; 20*4882a593Smuzhiyun xlnx,num-ss-bits = <0x1>; 21*4882a593Smuzhiyun xlnx,num-transfer-bits = <32>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24