1*4882a593Smuzhiyun* Socionext Synquacer HS-SPI bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun- compatible: should be "socionext,synquacer-spi" 5*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 6*4882a593Smuzhiyun region. 7*4882a593Smuzhiyun- interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts. 8*4882a593Smuzhiyun- clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK) 9*4882a593Smuzhiyun- clock-names: Shall be "iHCLK" and "iPCLK" respectively 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional Properties: 12*4882a593Smuzhiyun- socionext,use-rtm: boolean, if required to use "retimed clock" for RX 13*4882a593Smuzhiyun- socionext,set-aces: boolean, if same active clock edges field to be set. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun spi0: spi@ff110000 { 18*4882a593Smuzhiyun compatible = "socionext,synquacer-spi"; 19*4882a593Smuzhiyun reg = <0xff110000 0x1000>; 20*4882a593Smuzhiyun interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 21*4882a593Smuzhiyun <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 22*4882a593Smuzhiyun <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 23*4882a593Smuzhiyun clocks = <&clk_hsspi>; 24*4882a593Smuzhiyun clock-names = "iHCLK"; 25*4882a593Smuzhiyun socionext,use-rtm; 26*4882a593Smuzhiyun socionext,set-aces; 27*4882a593Smuzhiyun }; 28