1*4882a593SmuzhiyunSpreadtrum SPI Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "sprd,sc9860-spi". 5*4882a593Smuzhiyun- reg: Offset and length of SPI controller register space. 6*4882a593Smuzhiyun- interrupts: Should contain SPI interrupt. 7*4882a593Smuzhiyun- clock-names: Should contain following entries: 8*4882a593Smuzhiyun "spi" for SPI clock, 9*4882a593Smuzhiyun "source" for SPI source (parent) clock, 10*4882a593Smuzhiyun "enable" for SPI module enable clock. 11*4882a593Smuzhiyun- clocks: List of clock input name strings sorted in the same order 12*4882a593Smuzhiyun as the clock-names property. 13*4882a593Smuzhiyun- #address-cells: The number of cells required to define a chip select 14*4882a593Smuzhiyun address on the SPI bus. Should be set to 1. 15*4882a593Smuzhiyun- #size-cells: Should be set to 0. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyundma-names: Should contain names of the SPI used DMA channel. 19*4882a593Smuzhiyundmas: Should contain DMA channels and DMA slave ids which the SPI used 20*4882a593Smuzhiyun sorted in the same order as the dma-names property. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyunspi0: spi@70a00000{ 24*4882a593Smuzhiyun compatible = "sprd,sc9860-spi"; 25*4882a593Smuzhiyun reg = <0 0x70a00000 0 0x1000>; 26*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 27*4882a593Smuzhiyun clock-names = "spi", "source","enable"; 28*4882a593Smuzhiyun clocks = <&clk_spi0>, <&ext_26m>, <&clk_ap_apb_gates 5>; 29*4882a593Smuzhiyun dma-names = "rx_chn", "tx_chn"; 30*4882a593Smuzhiyun dmas = <&apdma 11 11>, <&apdma 12 12>; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <0>; 33*4882a593Smuzhiyun}; 34