1*4882a593SmuzhiyunSpreadtrum ADI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunADI is the abbreviation of Anolog-Digital interface, which is used to access 4*4882a593Smuzhiyunanalog chip (such as PMIC) from digital chip. ADI controller follows the SPI 5*4882a593Smuzhiyunframework for its hardware implementation is alike to SPI bus and its timing 6*4882a593Smuzhiyunis compatile to SPI timing. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunADI controller has 50 channels including 2 software read/write channels and 9*4882a593Smuzhiyun48 hardware channels to access analog chip. For 2 software read/write channels, 10*4882a593Smuzhiyunusers should set ADI registers to access analog chip. For hardware channels, 11*4882a593Smuzhiyunwe can configure them to allow other hardware components to use it independently, 12*4882a593Smuzhiyunwhich means we can just link one analog chip address to one hardware channel, 13*4882a593Smuzhiyunthen users can access the mapped analog chip address by this hardware channel 14*4882a593Smuzhiyuntriggered by hardware components instead of ADI software channels. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThus we introduce one property named "sprd,hw-channels" to configure hardware 17*4882a593Smuzhiyunchannels, the first value specifies the hardware channel id which is used to 18*4882a593Smuzhiyuntransfer data triggered by hardware automatically, and the second value specifies 19*4882a593Smuzhiyunthe analog chip address where user want to access by hardware components. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunSince we have multi-subsystems will use unique ADI to access analog chip, when 22*4882a593Smuzhiyunone system is reading/writing data by ADI software channels, that should be under 23*4882a593Smuzhiyunone hardware spinlock protection to prevent other systems from reading/writing 24*4882a593Smuzhiyundata by ADI software channels at the same time, or two parallel routine of setting 25*4882a593SmuzhiyunADI registers will make ADI controller registers chaos to lead incorrect results. 26*4882a593SmuzhiyunThen we need one hardware spinlock to synchronize between the multiple subsystems. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunThe new version ADI controller supplies multiple master channels for different 29*4882a593Smuzhiyunsubsystem accessing, that means no need to add hardware spinlock to synchronize, 30*4882a593Smuzhiyunthus change the hardware spinlock support to be optional to keep backward 31*4882a593Smuzhiyuncompatibility. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunRequired properties: 34*4882a593Smuzhiyun- compatible: Should be "sprd,sc9860-adi". 35*4882a593Smuzhiyun- reg: Offset and length of ADI-SPI controller register space. 36*4882a593Smuzhiyun- #address-cells: Number of cells required to define a chip select address 37*4882a593Smuzhiyun on the ADI-SPI bus. Should be set to 1. 38*4882a593Smuzhiyun- #size-cells: Size of cells required to define a chip select address size 39*4882a593Smuzhiyun on the ADI-SPI bus. Should be set to 0. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunOptional properties: 42*4882a593Smuzhiyun- hwlocks: Reference to a phandle of a hwlock provider node. 43*4882a593Smuzhiyun- hwlock-names: Reference to hwlock name strings defined in the same order 44*4882a593Smuzhiyun as the hwlocks, should be "adi". 45*4882a593Smuzhiyun- sprd,hw-channels: This is an array of channel values up to 49 channels. 46*4882a593Smuzhiyun The first value specifies the hardware channel id which is used to 47*4882a593Smuzhiyun transfer data triggered by hardware automatically, and the second 48*4882a593Smuzhiyun value specifies the analog chip address where user want to access 49*4882a593Smuzhiyun by hardware components. 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunSPI slave nodes must be children of the SPI controller node and can contain 52*4882a593Smuzhiyunproperties described in Documentation/devicetree/bindings/spi/spi-bus.txt. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExample: 55*4882a593Smuzhiyun adi_bus: spi@40030000 { 56*4882a593Smuzhiyun compatible = "sprd,sc9860-adi"; 57*4882a593Smuzhiyun reg = <0 0x40030000 0 0x10000>; 58*4882a593Smuzhiyun hwlocks = <&hwlock1 0>; 59*4882a593Smuzhiyun hwlock-names = "adi"; 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun sprd,hw-channels = <30 0x8c20>; 63*4882a593Smuzhiyun }; 64