1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-sifive.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: SiFive SPI controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Pragnesh Patel <pragnesh.patel@sifive.com> 11*4882a593Smuzhiyun - Paul Walmsley <paul.walmsley@sifive.com> 12*4882a593Smuzhiyun - Palmer Dabbelt <palmer@sifive.com> 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunallOf: 15*4882a593Smuzhiyun - $ref: "spi-controller.yaml#" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun items: 20*4882a593Smuzhiyun - const: sifive,fu540-c000-spi 21*4882a593Smuzhiyun - const: sifive,spi0 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun description: 24*4882a593Smuzhiyun Should be "sifive,<chip>-spi" and "sifive,spi<version>". 25*4882a593Smuzhiyun Supported compatible strings are - 26*4882a593Smuzhiyun "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated 27*4882a593Smuzhiyun onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive 28*4882a593Smuzhiyun SPI v0 IP block with no chip integration tweaks. 29*4882a593Smuzhiyun Please refer to sifive-blocks-ip-versioning.txt for details 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun SPI RTL that corresponds to the IP block version numbers can be found here - 32*4882a593Smuzhiyun https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reg: 35*4882a593Smuzhiyun minItems: 1 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - description: SPI registers region 38*4882a593Smuzhiyun - description: Memory mapped flash region 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupts: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clocks: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun Must reference the frequency given to the controller 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun sifive,fifo-depth: 50*4882a593Smuzhiyun description: 51*4882a593Smuzhiyun Depth of hardware queues; defaults to 8 52*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 53*4882a593Smuzhiyun enum: [8] 54*4882a593Smuzhiyun default: 8 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun sifive,max-bits-per-word: 57*4882a593Smuzhiyun description: 58*4882a593Smuzhiyun Maximum bits per word; defaults to 8 59*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 60*4882a593Smuzhiyun enum: [0, 1, 2, 3, 4, 5, 6, 7, 8] 61*4882a593Smuzhiyun default: 8 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunrequired: 64*4882a593Smuzhiyun - compatible 65*4882a593Smuzhiyun - reg 66*4882a593Smuzhiyun - interrupts 67*4882a593Smuzhiyun - clocks 68*4882a593Smuzhiyun 69*4882a593SmuzhiyununevaluatedProperties: false 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunexamples: 72*4882a593Smuzhiyun - | 73*4882a593Smuzhiyun spi: spi@10040000 { 74*4882a593Smuzhiyun compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 75*4882a593Smuzhiyun reg = <0x10040000 0x1000>, <0x20000000 0x10000000>; 76*4882a593Smuzhiyun interrupt-parent = <&plic>; 77*4882a593Smuzhiyun interrupts = <51>; 78*4882a593Smuzhiyun clocks = <&tlclk>; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <0>; 81*4882a593Smuzhiyun sifive,fifo-depth = <8>; 82*4882a593Smuzhiyun sifive,max-bits-per-word = <8>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun... 86