1*4882a593SmuzhiyunCavium, Inc. OCTEON SOC SPI master controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "cavium,octeon-3010-spi" 5*4882a593Smuzhiyun- reg : The register base for the controller. 6*4882a593Smuzhiyun- interrupts : One interrupt, used by the controller. 7*4882a593Smuzhiyun- #address-cells : <1>, as required by generic SPI binding. 8*4882a593Smuzhiyun- #size-cells : <0>, also as required by generic SPI binding. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunChild nodes as per the generic SPI binding. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunExample: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun spi@1070000001000 { 15*4882a593Smuzhiyun compatible = "cavium,octeon-3010-spi"; 16*4882a593Smuzhiyun reg = <0x10700 0x00001000 0x0 0x100>; 17*4882a593Smuzhiyun interrupts = <0 58>; 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun eeprom@0 { 22*4882a593Smuzhiyun compatible = "st,m95256", "atmel,at25"; 23*4882a593Smuzhiyun reg = <0>; 24*4882a593Smuzhiyun spi-max-frequency = <5000000>; 25*4882a593Smuzhiyun spi-cpha; 26*4882a593Smuzhiyun spi-cpol; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pagesize = <64>; 29*4882a593Smuzhiyun size = <32768>; 30*4882a593Smuzhiyun address-width = <16>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34