1*4882a593SmuzhiyunMacronix SPI controller Device Tree Bindings 2*4882a593Smuzhiyun-------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: should be "mxicy,mx25f0a-spi" 6*4882a593Smuzhiyun- #address-cells: should be 1 7*4882a593Smuzhiyun- #size-cells: should be 0 8*4882a593Smuzhiyun- reg: should contain 2 entries, one for the registers and one for the direct 9*4882a593Smuzhiyun mapping area 10*4882a593Smuzhiyun- reg-names: should contain "regs" and "dirmap" 11*4882a593Smuzhiyun- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk" 12*4882a593Smuzhiyun- clocks: should contain 3 entries for the "ps_clk", "send_clk" and 13*4882a593Smuzhiyun "send_dly_clk" clocks 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- interrupts: interrupt line connected to the SPI controller 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun spi@43c30000 { 21*4882a593Smuzhiyun compatible = "mxicy,mx25f0a-spi"; 22*4882a593Smuzhiyun reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>; 23*4882a593Smuzhiyun reg-names = "regs", "dirmap"; 24*4882a593Smuzhiyun clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>; 25*4882a593Smuzhiyun clock-names = "send_clk", "send_dly_clk", "ps_clk"; 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun flash@0 { 30*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 31*4882a593Smuzhiyun reg = <0>; 32*4882a593Smuzhiyun spi-max-frequency = <25000000>; 33*4882a593Smuzhiyun spi-tx-bus-width = <4>; 34*4882a593Smuzhiyun spi-rx-bus-width = <4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37