1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-mux.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Generic SPI Multiplexer 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This binding describes a SPI bus multiplexer to route the SPI chip select 11*4882a593Smuzhiyun signals. This can be used when you need more devices than the SPI controller 12*4882a593Smuzhiyun has chip selects available. An example setup is shown in ASCII art; the actual 13*4882a593Smuzhiyun setting of the multiplexer to a channel needs to be done by a specific SPI mux 14*4882a593Smuzhiyun driver. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun MOSI /--------------------------------+--------+--------+--------\ 17*4882a593Smuzhiyun MISO |/------------------------------+|-------+|-------+|-------\| 18*4882a593Smuzhiyun SCL ||/----------------------------+||------+||------+||------\|| 19*4882a593Smuzhiyun ||| ||| ||| ||| ||| 20*4882a593Smuzhiyun +------------+ ||| ||| ||| ||| 21*4882a593Smuzhiyun | SoC ||| | +-+++-+ +-+++-+ +-+++-+ +-+++-+ 22*4882a593Smuzhiyun | ||| | | dev | | dev | | dev | | dev | 23*4882a593Smuzhiyun | +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+ 24*4882a593Smuzhiyun | | SPI +-|-------+ Mux |\\ CS-0 | | | | 25*4882a593Smuzhiyun | +------+ | +--+---+\\\-------/ CS-1 | | | 26*4882a593Smuzhiyun | | | \\\----------------/ CS-2 | | 27*4882a593Smuzhiyun | +------+ | | \\-------------------------/ CS-3 | 28*4882a593Smuzhiyun | | ? +-|----------/ \----------------------------------/ 29*4882a593Smuzhiyun | +------+ | 30*4882a593Smuzhiyun +------------+ 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunallOf: 33*4882a593Smuzhiyun - $ref: "/schemas/spi/spi-controller.yaml#" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunmaintainers: 36*4882a593Smuzhiyun - Chris Packham <chris.packham@alliedtelesis.co.nz> 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunproperties: 39*4882a593Smuzhiyun compatible: 40*4882a593Smuzhiyun const: spi-mux 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun mux-controls: 43*4882a593Smuzhiyun maxItems: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunrequired: 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - spi-max-frequency 49*4882a593Smuzhiyun - mux-controls 50*4882a593Smuzhiyun 51*4882a593SmuzhiyununevaluatedProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 56*4882a593Smuzhiyun mux: mux-controller { 57*4882a593Smuzhiyun compatible = "gpio-mux"; 58*4882a593Smuzhiyun #mux-control-cells = <0>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun mux-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun spi { 64*4882a593Smuzhiyun #address-cells = <1>; 65*4882a593Smuzhiyun #size-cells = <0>; 66*4882a593Smuzhiyun spi@0 { 67*4882a593Smuzhiyun compatible = "spi-mux"; 68*4882a593Smuzhiyun reg = <0>; 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun spi-max-frequency = <100000000>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun mux-controls = <&mux>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun spi-flash@0 { 76*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun #address-cells = <1>; 79*4882a593Smuzhiyun #size-cells = <0>; 80*4882a593Smuzhiyun spi-max-frequency = <40000000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun spi-device@1 { 84*4882a593Smuzhiyun compatible = "lineartechnology,ltc2488"; 85*4882a593Smuzhiyun reg = <1>; 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun spi-max-frequency = <10000000>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92