1*4882a593Smuzhiyun* Freescale Quad Serial Peripheral Interface(QuadSPI) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", 5*4882a593Smuzhiyun "fsl,imx7d-qspi", "fsl,imx6ul-qspi", 6*4882a593Smuzhiyun "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" 7*4882a593Smuzhiyun or 8*4882a593Smuzhiyun "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" 9*4882a593Smuzhiyun - reg : the first contains the register location and length, 10*4882a593Smuzhiyun the second contains the memory mapping address and length 11*4882a593Smuzhiyun - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" 12*4882a593Smuzhiyun - interrupts : Should contain the interrupt for the device 13*4882a593Smuzhiyun - clocks : The clocks needed by the QuadSPI controller 14*4882a593Smuzhiyun - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired SPI slave node properties: 17*4882a593Smuzhiyun - reg: There are two buses (A and B) with two chip selects each. 18*4882a593Smuzhiyun This encodes to which bus and CS the flash is connected: 19*4882a593Smuzhiyun <0>: Bus A, CS 0 20*4882a593Smuzhiyun <1>: Bus A, CS 1 21*4882a593Smuzhiyun <2>: Bus B, CS 0 22*4882a593Smuzhiyun <3>: Bus B, CS 1 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunqspi0: quadspi@40044000 { 27*4882a593Smuzhiyun compatible = "fsl,vf610-qspi"; 28*4882a593Smuzhiyun reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; 29*4882a593Smuzhiyun reg-names = "QuadSPI", "QuadSPI-memory"; 30*4882a593Smuzhiyun interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 31*4882a593Smuzhiyun clocks = <&clks VF610_CLK_QSPI0_EN>, 32*4882a593Smuzhiyun <&clks VF610_CLK_QSPI0>; 33*4882a593Smuzhiyun clock-names = "qspi_en", "qspi"; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun flash0: s25fl128s@0 { 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun compatible = "spansion,s25fl128s", "jedec,spi-nor"; 39*4882a593Smuzhiyun spi-max-frequency = <50000000>; 40*4882a593Smuzhiyun reg = <0>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunExample showing the usage of two SPI NOR devices on bus A: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&qspi2 { 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_qspi2>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun flash0: n25q256a@0 { 52*4882a593Smuzhiyun #address-cells = <1>; 53*4882a593Smuzhiyun #size-cells = <1>; 54*4882a593Smuzhiyun compatible = "micron,n25q256a", "jedec,spi-nor"; 55*4882a593Smuzhiyun spi-max-frequency = <29000000>; 56*4882a593Smuzhiyun reg = <0>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun flash1: n25q256a@1 { 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <1>; 62*4882a593Smuzhiyun compatible = "micron,n25q256a", "jedec,spi-nor"; 63*4882a593Smuzhiyun spi-max-frequency = <29000000>; 64*4882a593Smuzhiyun reg = <1>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun}; 67