1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale Low Power SPI (LPSPI) for i.MX 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "/schemas/spi/spi-controller.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - fsl,imx7ulp-spi 19*4882a593Smuzhiyun - fsl,imx8qxp-spi 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupts: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - description: SoC SPI per clock 30*4882a593Smuzhiyun - description: SoC SPI ipg clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: per 35*4882a593Smuzhiyun - const: ipg 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun fsl,spi-only-use-cs1-sel: 38*4882a593Smuzhiyun description: 39*4882a593Smuzhiyun spi common code does not support use of CS signals discontinuously. 40*4882a593Smuzhiyun i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add 41*4882a593Smuzhiyun this property to re-config the chipselect value in the LPSPI driver. 42*4882a593Smuzhiyun type: boolean 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunrequired: 45*4882a593Smuzhiyun - compatible 46*4882a593Smuzhiyun - reg 47*4882a593Smuzhiyun - interrupts 48*4882a593Smuzhiyun - clocks 49*4882a593Smuzhiyun - clock-names 50*4882a593Smuzhiyun 51*4882a593SmuzhiyununevaluatedProperties: false 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun #include <dt-bindings/clock/imx7ulp-clock.h> 56*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun spi@40290000 { 59*4882a593Smuzhiyun compatible = "fsl,imx7ulp-spi"; 60*4882a593Smuzhiyun reg = <0x40290000 0x10000>; 61*4882a593Smuzhiyun interrupt-parent = <&intc>; 62*4882a593Smuzhiyun interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 63*4882a593Smuzhiyun clocks = <&clks IMX7ULP_CLK_LPSPI2>, 64*4882a593Smuzhiyun <&clks IMX7ULP_CLK_DUMMY>; 65*4882a593Smuzhiyun clock-names = "per", "ipg"; 66*4882a593Smuzhiyun spi-slave; 67*4882a593Smuzhiyun fsl,spi-only-use-cs1-sel; 68*4882a593Smuzhiyun }; 69