1*4882a593SmuzhiyunARM Freescale DSPI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : must be one of: 5*4882a593Smuzhiyun "fsl,vf610-dspi", 6*4882a593Smuzhiyun "fsl,ls1021a-v1.0-dspi", 7*4882a593Smuzhiyun "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 8*4882a593Smuzhiyun "fsl,ls1028a-dspi", 9*4882a593Smuzhiyun "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 10*4882a593Smuzhiyun "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 11*4882a593Smuzhiyun "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 12*4882a593Smuzhiyun "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), 13*4882a593Smuzhiyun "fsl,ls2085a-dspi", 14*4882a593Smuzhiyun "fsl,lx2160a-dspi", 15*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 16*4882a593Smuzhiyun- interrupts : Should contain SPI controller interrupt 17*4882a593Smuzhiyun- clocks: from common clock binding: handle to dspi clock. 18*4882a593Smuzhiyun- clock-names: from common clock binding: Shall be "dspi". 19*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 20*4882a593Smuzhiyun- pinctrl-names: must contain a "default" entry. 21*4882a593Smuzhiyun- spi-num-chipselects : the number of the chipselect signals. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional property: 24*4882a593Smuzhiyun- big-endian: If present the dspi device's registers are implemented 25*4882a593Smuzhiyun in big endian mode. 26*4882a593Smuzhiyun- bus-num : the slave chip chipselect signal number. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunOptional SPI slave node properties: 29*4882a593Smuzhiyun- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip 30*4882a593Smuzhiyun select and the start of clock signal, at the start of a transfer. 31*4882a593Smuzhiyun- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock 32*4882a593Smuzhiyun signal and deactivating chip select, at the end of a transfer. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyundspi0@4002c000 { 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun compatible = "fsl,vf610-dspi"; 40*4882a593Smuzhiyun reg = <0x4002c000 0x1000>; 41*4882a593Smuzhiyun interrupts = <0 67 0x04>; 42*4882a593Smuzhiyun clocks = <&clks VF610_CLK_DSPI0>; 43*4882a593Smuzhiyun clock-names = "dspi"; 44*4882a593Smuzhiyun spi-num-chipselects = <5>; 45*4882a593Smuzhiyun bus-num = <0>; 46*4882a593Smuzhiyun pinctrl-names = "default"; 47*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_dspi0_1>; 48*4882a593Smuzhiyun big-endian; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun sflash: at26df081a@0 { 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <1>; 53*4882a593Smuzhiyun compatible = "atmel,at26df081a"; 54*4882a593Smuzhiyun spi-max-frequency = <16000000>; 55*4882a593Smuzhiyun spi-cpol; 56*4882a593Smuzhiyun spi-cpha; 57*4882a593Smuzhiyun reg = <0>; 58*4882a593Smuzhiyun linux,modalias = "m25p80"; 59*4882a593Smuzhiyun modal = "at26df081a"; 60*4882a593Smuzhiyun fsl,spi-cs-sck-delay = <100>; 61*4882a593Smuzhiyun fsl,spi-sck-cs-delay = <50>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66