1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Rockchip Serial Flash Controller (SFC) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Heiko Stuebner <heiko@sntech.de> 11*4882a593Smuzhiyun - Chris Morgan <macromorgan@hotmail.com> 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunallOf: 14*4882a593Smuzhiyun - $ref: spi-controller.yaml# 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: rockchip,sfc 19*4882a593Smuzhiyun description: 20*4882a593Smuzhiyun The rockchip sfc controller is a standalone IP with version register, 21*4882a593Smuzhiyun and the driver can handle all the feature difference inside the IP 22*4882a593Smuzhiyun depending on the version register. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupts: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - description: Bus Clock 33*4882a593Smuzhiyun - description: Module Clock 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock-names: 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - const: clk_sfc 38*4882a593Smuzhiyun - const: hclk_sfc 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun power-domains: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun rockchip,sfc-no-dma: 44*4882a593Smuzhiyun description: Disable DMA and utilize FIFO mode only 45*4882a593Smuzhiyun type: boolean 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunpatternProperties: 48*4882a593Smuzhiyun "^flash@[0-3]$": 49*4882a593Smuzhiyun type: object 50*4882a593Smuzhiyun properties: 51*4882a593Smuzhiyun reg: 52*4882a593Smuzhiyun minimum: 0 53*4882a593Smuzhiyun maximum: 3 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunrequired: 56*4882a593Smuzhiyun - compatible 57*4882a593Smuzhiyun - reg 58*4882a593Smuzhiyun - interrupts 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun - clock-names 61*4882a593Smuzhiyun 62*4882a593SmuzhiyununevaluatedProperties: false 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunexamples: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun #include <dt-bindings/clock/px30-cru.h> 67*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 68*4882a593Smuzhiyun #include <dt-bindings/power/px30-power.h> 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun sfc: spi@ff3a0000 { 71*4882a593Smuzhiyun compatible = "rockchip,sfc"; 72*4882a593Smuzhiyun reg = <0xff3a0000 0x4000>; 73*4882a593Smuzhiyun interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 74*4882a593Smuzhiyun clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 75*4882a593Smuzhiyun clock-names = "clk_sfc", "hclk_sfc"; 76*4882a593Smuzhiyun pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun power-domains = <&power PX30_PD_MMC_NAND>; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <0>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun flash@0 { 83*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 84*4882a593Smuzhiyun reg = <0>; 85*4882a593Smuzhiyun spi-max-frequency = <108000000>; 86*4882a593Smuzhiyun spi-rx-bus-width = <2>; 87*4882a593Smuzhiyun spi-tx-bus-width = <2>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun... 92