1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas MSIOF SPI controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: spi-controller.yaml# 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun oneOf: 18*4882a593Smuzhiyun - items: 19*4882a593Smuzhiyun - const: renesas,msiof-sh73a0 # SH-Mobile AG5 20*4882a593Smuzhiyun - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible 21*4882a593Smuzhiyun # device 22*4882a593Smuzhiyun - items: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - renesas,msiof-r8a7742 # RZ/G1H 25*4882a593Smuzhiyun - renesas,msiof-r8a7743 # RZ/G1M 26*4882a593Smuzhiyun - renesas,msiof-r8a7744 # RZ/G1N 27*4882a593Smuzhiyun - renesas,msiof-r8a7745 # RZ/G1E 28*4882a593Smuzhiyun - renesas,msiof-r8a77470 # RZ/G1C 29*4882a593Smuzhiyun - renesas,msiof-r8a7790 # R-Car H2 30*4882a593Smuzhiyun - renesas,msiof-r8a7791 # R-Car M2-W 31*4882a593Smuzhiyun - renesas,msiof-r8a7792 # R-Car V2H 32*4882a593Smuzhiyun - renesas,msiof-r8a7793 # R-Car M2-N 33*4882a593Smuzhiyun - renesas,msiof-r8a7794 # R-Car E2 34*4882a593Smuzhiyun - const: renesas,rcar-gen2-msiof # generic R-Car Gen2 and RZ/G1 35*4882a593Smuzhiyun # compatible device 36*4882a593Smuzhiyun - items: 37*4882a593Smuzhiyun - enum: 38*4882a593Smuzhiyun - renesas,msiof-r8a774a1 # RZ/G2M 39*4882a593Smuzhiyun - renesas,msiof-r8a774b1 # RZ/G2N 40*4882a593Smuzhiyun - renesas,msiof-r8a774c0 # RZ/G2E 41*4882a593Smuzhiyun - renesas,msiof-r8a774e1 # RZ/G2H 42*4882a593Smuzhiyun - renesas,msiof-r8a7795 # R-Car H3 43*4882a593Smuzhiyun - renesas,msiof-r8a7796 # R-Car M3-W 44*4882a593Smuzhiyun - renesas,msiof-r8a77961 # R-Car M3-W+ 45*4882a593Smuzhiyun - renesas,msiof-r8a77965 # R-Car M3-N 46*4882a593Smuzhiyun - renesas,msiof-r8a77970 # R-Car V3M 47*4882a593Smuzhiyun - renesas,msiof-r8a77980 # R-Car V3H 48*4882a593Smuzhiyun - renesas,msiof-r8a77990 # R-Car E3 49*4882a593Smuzhiyun - renesas,msiof-r8a77995 # R-Car D3 50*4882a593Smuzhiyun - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2 51*4882a593Smuzhiyun # compatible device 52*4882a593Smuzhiyun - items: 53*4882a593Smuzhiyun - const: renesas,sh-msiof # deprecated 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun reg: 56*4882a593Smuzhiyun minItems: 1 57*4882a593Smuzhiyun maxItems: 2 58*4882a593Smuzhiyun oneOf: 59*4882a593Smuzhiyun - items: 60*4882a593Smuzhiyun - description: CPU and DMA engine registers 61*4882a593Smuzhiyun - items: 62*4882a593Smuzhiyun - description: CPU registers 63*4882a593Smuzhiyun - description: DMA engine registers 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun interrupts: 66*4882a593Smuzhiyun maxItems: 1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun clocks: 69*4882a593Smuzhiyun maxItems: 1 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun num-cs: 72*4882a593Smuzhiyun description: | 73*4882a593Smuzhiyun Total number of chip selects (default is 1). 74*4882a593Smuzhiyun Up to 3 native chip selects are supported: 75*4882a593Smuzhiyun 0: MSIOF_SYNC 76*4882a593Smuzhiyun 1: MSIOF_SS1 77*4882a593Smuzhiyun 2: MSIOF_SS2 78*4882a593Smuzhiyun Hardware limitations related to chip selects: 79*4882a593Smuzhiyun - Native chip selects are always deasserted in between transfers 80*4882a593Smuzhiyun that are part of the same message. Use cs-gpios to work around 81*4882a593Smuzhiyun this. 82*4882a593Smuzhiyun - All slaves using native chip selects must use the same spi-cs-high 83*4882a593Smuzhiyun configuration. Use cs-gpios to work around this. 84*4882a593Smuzhiyun - When using GPIO chip selects, at least one native chip select must 85*4882a593Smuzhiyun be left unused, as it will be driven anyway. 86*4882a593Smuzhiyun minimum: 1 87*4882a593Smuzhiyun maximum: 3 88*4882a593Smuzhiyun default: 1 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun dmas: 91*4882a593Smuzhiyun minItems: 2 92*4882a593Smuzhiyun maxItems: 4 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun dma-names: 95*4882a593Smuzhiyun minItems: 2 96*4882a593Smuzhiyun maxItems: 4 97*4882a593Smuzhiyun items: 98*4882a593Smuzhiyun enum: [ tx, rx ] 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun renesas,dtdl: 101*4882a593Smuzhiyun description: delay sync signal (setup) in transmit mode. 102*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 103*4882a593Smuzhiyun enum: 104*4882a593Smuzhiyun - 0 # no bit delay 105*4882a593Smuzhiyun - 50 # 0.5-clock-cycle delay 106*4882a593Smuzhiyun - 100 # 1-clock-cycle delay 107*4882a593Smuzhiyun - 150 # 1.5-clock-cycle delay 108*4882a593Smuzhiyun - 200 # 2-clock-cycle delay 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun renesas,syncdl: 111*4882a593Smuzhiyun description: delay sync signal (hold) in transmit mode 112*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 113*4882a593Smuzhiyun enum: 114*4882a593Smuzhiyun - 0 # no bit delay 115*4882a593Smuzhiyun - 50 # 0.5-clock-cycle delay 116*4882a593Smuzhiyun - 100 # 1-clock-cycle delay 117*4882a593Smuzhiyun - 150 # 1.5-clock-cycle delay 118*4882a593Smuzhiyun - 200 # 2-clock-cycle delay 119*4882a593Smuzhiyun - 300 # 3-clock-cycle delay 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun renesas,tx-fifo-size: 122*4882a593Smuzhiyun # deprecated for soctype-specific bindings 123*4882a593Smuzhiyun description: | 124*4882a593Smuzhiyun Override the default TX fifo size. Unit is words. Ignored if 0. 125*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 126*4882a593Smuzhiyun maxItems: 1 127*4882a593Smuzhiyun default: 64 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun renesas,rx-fifo-size: 130*4882a593Smuzhiyun # deprecated for soctype-specific bindings 131*4882a593Smuzhiyun description: | 132*4882a593Smuzhiyun Override the default RX fifo size. Unit is words. Ignored if 0. 133*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 134*4882a593Smuzhiyun maxItems: 1 135*4882a593Smuzhiyun default: 64 136*4882a593Smuzhiyun 137*4882a593Smuzhiyunrequired: 138*4882a593Smuzhiyun - compatible 139*4882a593Smuzhiyun - reg 140*4882a593Smuzhiyun - interrupts 141*4882a593Smuzhiyun - '#address-cells' 142*4882a593Smuzhiyun - '#size-cells' 143*4882a593Smuzhiyun 144*4882a593SmuzhiyununevaluatedProperties: false 145*4882a593Smuzhiyun 146*4882a593Smuzhiyunexamples: 147*4882a593Smuzhiyun - | 148*4882a593Smuzhiyun #include <dt-bindings/clock/r8a7791-clock.h> 149*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun msiof0: spi@e6e20000 { 152*4882a593Smuzhiyun compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof"; 153*4882a593Smuzhiyun reg = <0xe6e20000 0x0064>; 154*4882a593Smuzhiyun interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 155*4882a593Smuzhiyun clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 156*4882a593Smuzhiyun dmas = <&dmac0 0x51>, <&dmac0 0x52>; 157*4882a593Smuzhiyun dma-names = "tx", "rx"; 158*4882a593Smuzhiyun #address-cells = <1>; 159*4882a593Smuzhiyun #size-cells = <0>; 160*4882a593Smuzhiyun }; 161