1*4882a593SmuzhiyunGENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe QUP v3 core is a GENI based AHB slave that provides a common data path 4*4882a593Smuzhiyun(an output FIFO and an input FIFO) for serial peripheral interface (SPI) 5*4882a593Smuzhiyunmini-core. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunSPI in master mode supports up to 50MHz, up to four chip selects, programmable 8*4882a593Smuzhiyundata path from 4 bits to 32 bits and numerous protocol variants. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: Must contain "qcom,geni-spi". 12*4882a593Smuzhiyun- reg: Must contain SPI register location and length. 13*4882a593Smuzhiyun- interrupts: Must contain SPI controller interrupts. 14*4882a593Smuzhiyun- clock-names: Must contain "se". 15*4882a593Smuzhiyun- clocks: Serial engine core clock needed by the device. 16*4882a593Smuzhiyun- #address-cells: Must be <1> to define a chip select address on 17*4882a593Smuzhiyun the SPI bus. 18*4882a593Smuzhiyun- #size-cells: Must be <0>. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunSPI Controller nodes must be child of GENI based Qualcomm Universal 21*4882a593SmuzhiyunPeripharal. Please refer GENI based QUP wrapper controller node bindings 22*4882a593Smuzhiyundescribed in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunSPI slave nodes must be children of the SPI master node and conform to SPI bus 25*4882a593Smuzhiyunbinding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun spi0: spi@a84000 { 29*4882a593Smuzhiyun compatible = "qcom,geni-spi"; 30*4882a593Smuzhiyun reg = <0xa84000 0x4000>; 31*4882a593Smuzhiyun interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 32*4882a593Smuzhiyun clock-names = "se"; 33*4882a593Smuzhiyun clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; 34*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 35*4882a593Smuzhiyun pinctrl-0 = <&qup_1_spi_2_active>; 36*4882a593Smuzhiyun pinctrl-1 = <&qup_1_spi_2_sleep>; 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun }; 40