1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Qualcomm Quad Serial Peripheral Interface (QSPI) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Mukesh Savaliya <msavaliy@codeaurora.org> 12*4882a593Smuzhiyun - Akash Asthana <akashast@codeaurora.org> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: The QSPI controller allows SPI protocol communication in single, 15*4882a593Smuzhiyun dual, or quad wire transmission modes for read/write access to slaves such 16*4882a593Smuzhiyun as NOR flash. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunallOf: 19*4882a593Smuzhiyun - $ref: /spi/spi-controller.yaml# 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun items: 24*4882a593Smuzhiyun - const: qcom,sdm845-qspi 25*4882a593Smuzhiyun - const: qcom,qspi-v1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clock-names: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - const: iface 36*4882a593Smuzhiyun - const: core 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks: 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - description: AHB clock 41*4882a593Smuzhiyun - description: QSPI core clock 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun interconnects: 44*4882a593Smuzhiyun minItems: 1 45*4882a593Smuzhiyun maxItems: 2 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interconnect-names: 48*4882a593Smuzhiyun minItems: 1 49*4882a593Smuzhiyun items: 50*4882a593Smuzhiyun - const: qspi-config 51*4882a593Smuzhiyun - const: qspi-memory 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunrequired: 54*4882a593Smuzhiyun - compatible 55*4882a593Smuzhiyun - reg 56*4882a593Smuzhiyun - interrupts 57*4882a593Smuzhiyun - clock-names 58*4882a593Smuzhiyun - clocks 59*4882a593Smuzhiyun 60*4882a593SmuzhiyununevaluatedProperties: false 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunexamples: 63*4882a593Smuzhiyun - | 64*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-sdm845.h> 65*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun soc: soc { 68*4882a593Smuzhiyun #address-cells = <2>; 69*4882a593Smuzhiyun #size-cells = <2>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun qspi: spi@88df000 { 72*4882a593Smuzhiyun compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 73*4882a593Smuzhiyun reg = <0 0x88df000 0 0x600>; 74*4882a593Smuzhiyun #address-cells = <1>; 75*4882a593Smuzhiyun #size-cells = <0>; 76*4882a593Smuzhiyun interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 77*4882a593Smuzhiyun clock-names = "iface", "core"; 78*4882a593Smuzhiyun clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 79*4882a593Smuzhiyun <&gcc GCC_QSPI_CORE_CLK>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun flash@0 { 82*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 83*4882a593Smuzhiyun reg = <0>; 84*4882a593Smuzhiyun spi-max-frequency = <25000000>; 85*4882a593Smuzhiyun spi-tx-bus-width = <2>; 86*4882a593Smuzhiyun spi-rx-bus-width = <2>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun... 92