1*4882a593SmuzhiyunNVIDIA Tegra20 SFLASH controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be "nvidia,tegra20-sflash". 5*4882a593Smuzhiyun- reg: Should contain SFLASH registers location and length. 6*4882a593Smuzhiyun- interrupts: Should contain SFLASH interrupts. 7*4882a593Smuzhiyun- clocks : Must contain one entry, for the module clock. 8*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 9*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 10*4882a593Smuzhiyun See ../reset/reset.txt for details. 11*4882a593Smuzhiyun- reset-names : Must include the following entries: 12*4882a593Smuzhiyun - spi 13*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in clock-names. 14*4882a593Smuzhiyun See ../dma/dma.txt for details. 15*4882a593Smuzhiyun- dma-names : Must include the following entries: 16*4882a593Smuzhiyun - rx 17*4882a593Smuzhiyun - tx 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRecommended properties: 20*4882a593Smuzhiyun- spi-max-frequency: Definition as per 21*4882a593Smuzhiyun Documentation/devicetree/bindings/spi/spi-bus.txt 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunspi@7000c380 { 26*4882a593Smuzhiyun compatible = "nvidia,tegra20-sflash"; 27*4882a593Smuzhiyun reg = <0x7000c380 0x80>; 28*4882a593Smuzhiyun interrupts = <0 39 0x04>; 29*4882a593Smuzhiyun spi-max-frequency = <25000000>; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <0>; 32*4882a593Smuzhiyun clocks = <&tegra_car 43>; 33*4882a593Smuzhiyun resets = <&tegra_car 43>; 34*4882a593Smuzhiyun reset-names = "spi"; 35*4882a593Smuzhiyun dmas = <&apbdma 11>, <&apbdma 11>; 36*4882a593Smuzhiyun dma-names = "rx", "tx"; 37*4882a593Smuzhiyun}; 38