1*4882a593SmuzhiyunNVIDIA Tegra114 SPI controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra114, must contain "nvidia,tegra114-spi". 5*4882a593Smuzhiyun Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where 6*4882a593Smuzhiyun <chip> is tegra124, tegra132, or tegra210. 7*4882a593Smuzhiyun- reg: Should contain SPI registers location and length. 8*4882a593Smuzhiyun- interrupts: Should contain SPI interrupts. 9*4882a593Smuzhiyun- clock-names : Must include the following entries: 10*4882a593Smuzhiyun - spi 11*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 12*4882a593Smuzhiyun See ../reset/reset.txt for details. 13*4882a593Smuzhiyun- reset-names : Must include the following entries: 14*4882a593Smuzhiyun - spi 15*4882a593Smuzhiyun- dmas : Must contain an entry for each entry in clock-names. 16*4882a593Smuzhiyun See ../dma/dma.txt for details. 17*4882a593Smuzhiyun- dma-names : Must include the following entries: 18*4882a593Smuzhiyun - rx 19*4882a593Smuzhiyun - tx 20*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names. 21*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunRecommended properties: 24*4882a593Smuzhiyun- spi-max-frequency: Definition as per 25*4882a593Smuzhiyun Documentation/devicetree/bindings/spi/spi-bus.txt 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device 28*4882a593Smuzhiyun with this tap value. This property is used to tune the outgoing data from 29*4882a593Smuzhiyun Tegra SPI master with respect to outgoing Tegra SPI master clock. 30*4882a593Smuzhiyun Tap values vary based on the platform design trace lengths from Tegra SPI 31*4882a593Smuzhiyun to corresponding slave devices. Valid tap values are from 0 thru 63. 32*4882a593Smuzhiyun- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device 33*4882a593Smuzhiyun with this tap value. This property is used to adjust the Tegra SPI master 34*4882a593Smuzhiyun clock with respect to the data from the SPI slave device. 35*4882a593Smuzhiyun Tap values vary based on the platform design trace lengths from Tegra SPI 36*4882a593Smuzhiyun to corresponding slave devices. Valid tap values are from 0 thru 63. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExample: 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunspi@7000d600 { 41*4882a593Smuzhiyun compatible = "nvidia,tegra114-spi"; 42*4882a593Smuzhiyun reg = <0x7000d600 0x200>; 43*4882a593Smuzhiyun interrupts = <0 82 0x04>; 44*4882a593Smuzhiyun spi-max-frequency = <25000000>; 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <0>; 47*4882a593Smuzhiyun clocks = <&tegra_car 44>; 48*4882a593Smuzhiyun clock-names = "spi"; 49*4882a593Smuzhiyun resets = <&tegra_car 44>; 50*4882a593Smuzhiyun reset-names = "spi"; 51*4882a593Smuzhiyun dmas = <&apbdma 16>, <&apbdma 16>; 52*4882a593Smuzhiyun dma-names = "rx", "tx"; 53*4882a593Smuzhiyun <spi-client>@<bus_num> { 54*4882a593Smuzhiyun ... 55*4882a593Smuzhiyun ... 56*4882a593Smuzhiyun nvidia,rx-clk-tap-delay = <0>; 57*4882a593Smuzhiyun nvidia,tx-clk-tap-delay = <16>; 58*4882a593Smuzhiyun ... 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun}; 62