1*4882a593SmuzhiyunNuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunNuvoton NPCM7xx SOC support two PSPI channels. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC 7*4882a593Smuzhiyun - #address-cells : should be 1. see spi-bus.txt 8*4882a593Smuzhiyun - #size-cells : should be 0. see spi-bus.txt 9*4882a593Smuzhiyun - specifies physical base address and size of the register. 10*4882a593Smuzhiyun - interrupts : contain PSPI interrupt. 11*4882a593Smuzhiyun - clocks : phandle of PSPI reference clock. 12*4882a593Smuzhiyun - clock-names: Should be "clk_apb5". 13*4882a593Smuzhiyun - pinctrl-names : a pinctrl state named "default" must be defined. 14*4882a593Smuzhiyun - pinctrl-0 : phandle referencing pin configuration of the device. 15*4882a593Smuzhiyun - resets : phandle to the reset control for this device. 16*4882a593Smuzhiyun - cs-gpios: Specifies the gpio pins to be used for chipselects. 17*4882a593Smuzhiyun See: Documentation/devicetree/bindings/spi/spi-bus.txt 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- clock-frequency : Input clock frequency to the PSPI block in Hz. 21*4882a593Smuzhiyun Default is 25000000 Hz. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunspi0: spi@f0200000 { 24*4882a593Smuzhiyun compatible = "nuvoton,npcm750-pspi"; 25*4882a593Smuzhiyun reg = <0xf0200000 0x1000>; 26*4882a593Smuzhiyun pinctrl-names = "default"; 27*4882a593Smuzhiyun pinctrl-0 = <&pspi1_pins>; 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 31*4882a593Smuzhiyun clocks = <&clk NPCM7XX_CLK_APB5>; 32*4882a593Smuzhiyun clock-names = "clk_apb5"; 33*4882a593Smuzhiyun resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1> 34*4882a593Smuzhiyun cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 35*4882a593Smuzhiyun}; 36