1*4882a593SmuzhiyunMicrochip PIC32 SPI Master controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "microchip,pic32mzda-spi". 5*4882a593Smuzhiyun- reg: Address and length of register space for the device. 6*4882a593Smuzhiyun- interrupts: Should contain all three spi interrupts in sequence 7*4882a593Smuzhiyun of <fault-irq>, <receive-irq>, <transmit-irq>. 8*4882a593Smuzhiyun- interrupt-names: Should be "fault", "rx", "tx" in order. 9*4882a593Smuzhiyun- clocks: Phandle of the clock generating SPI clock on the bus. 10*4882a593Smuzhiyun- clock-names: Should be "mck0". 11*4882a593Smuzhiyun- cs-gpios: Specifies the gpio pins to be used for chipselects. 12*4882a593Smuzhiyun See: Documentation/devicetree/bindings/spi/spi-bus.txt 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunOptional properties: 15*4882a593Smuzhiyun- dmas: Two or more DMA channel specifiers following the convention outlined 16*4882a593Smuzhiyun in Documentation/devicetree/bindings/dma/dma.txt 17*4882a593Smuzhiyun- dma-names: Names for the dma channels. There must be at least one channel 18*4882a593Smuzhiyun named "spi-tx" for transmit and named "spi-rx" for receive. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunspi1: spi@1f821000 { 23*4882a593Smuzhiyun compatible = "microchip,pic32mzda-spi"; 24*4882a593Smuzhiyun reg = <0x1f821000 0x200>; 25*4882a593Smuzhiyun interrupts = <109 IRQ_TYPE_LEVEL_HIGH>, 26*4882a593Smuzhiyun <110 IRQ_TYPE_LEVEL_HIGH>, 27*4882a593Smuzhiyun <111 IRQ_TYPE_LEVEL_HIGH>; 28*4882a593Smuzhiyun interrupt-names = "fault", "rx", "tx"; 29*4882a593Smuzhiyun clocks = <&PBCLK2>; 30*4882a593Smuzhiyun clock-names = "mck0"; 31*4882a593Smuzhiyun cs-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; 32*4882a593Smuzhiyun dmas = <&dma 134>, <&dma 135>; 33*4882a593Smuzhiyun dma-names = "spi-rx", "spi-tx"; 34*4882a593Smuzhiyun}; 35