xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Serial NOR flash controller for MediaTek ARM SoCs
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Bayi Cheng <bayi.cheng@mediatek.com>
11*4882a593Smuzhiyun  - Chuanhong Guo <gch981213@gmail.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  This spi controller support single, dual, or quad mode transfer for
15*4882a593Smuzhiyun  SPI NOR flash. There should be only one spi slave device following
16*4882a593Smuzhiyun  generic spi bindings. It's not recommended to use this controller
17*4882a593Smuzhiyun  for devices other than SPI NOR flash due to limited transfer
18*4882a593Smuzhiyun  capability of this controller.
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunallOf:
21*4882a593Smuzhiyun  - $ref: /spi/spi-controller.yaml#
22*4882a593Smuzhiyun
23*4882a593Smuzhiyunproperties:
24*4882a593Smuzhiyun  compatible:
25*4882a593Smuzhiyun    oneOf:
26*4882a593Smuzhiyun      - items:
27*4882a593Smuzhiyun          - enum:
28*4882a593Smuzhiyun              - mediatek,mt2701-nor
29*4882a593Smuzhiyun              - mediatek,mt2712-nor
30*4882a593Smuzhiyun              - mediatek,mt7622-nor
31*4882a593Smuzhiyun              - mediatek,mt7623-nor
32*4882a593Smuzhiyun              - mediatek,mt7629-nor
33*4882a593Smuzhiyun              - mediatek,mt8192-nor
34*4882a593Smuzhiyun          - enum:
35*4882a593Smuzhiyun              - mediatek,mt8173-nor
36*4882a593Smuzhiyun      - items:
37*4882a593Smuzhiyun          - const: mediatek,mt8173-nor
38*4882a593Smuzhiyun  reg:
39*4882a593Smuzhiyun    maxItems: 1
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  interrupts:
42*4882a593Smuzhiyun    maxItems: 1
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  clocks:
45*4882a593Smuzhiyun    items:
46*4882a593Smuzhiyun      - description: clock used for spi bus
47*4882a593Smuzhiyun      - description: clock used for controller
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  clock-names:
50*4882a593Smuzhiyun    items:
51*4882a593Smuzhiyun      - const: spi
52*4882a593Smuzhiyun      - const: sf
53*4882a593Smuzhiyun
54*4882a593Smuzhiyunrequired:
55*4882a593Smuzhiyun  - compatible
56*4882a593Smuzhiyun  - reg
57*4882a593Smuzhiyun  - interrupts
58*4882a593Smuzhiyun  - clocks
59*4882a593Smuzhiyun  - clock-names
60*4882a593Smuzhiyun
61*4882a593SmuzhiyununevaluatedProperties: false
62*4882a593Smuzhiyun
63*4882a593Smuzhiyunexamples:
64*4882a593Smuzhiyun  - |
65*4882a593Smuzhiyun    #include <dt-bindings/clock/mt8173-clk.h>
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun    soc {
68*4882a593Smuzhiyun      #address-cells = <2>;
69*4882a593Smuzhiyun      #size-cells = <2>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun      nor_flash: spi@1100d000 {
72*4882a593Smuzhiyun        compatible = "mediatek,mt8173-nor";
73*4882a593Smuzhiyun        reg = <0 0x1100d000 0 0xe0>;
74*4882a593Smuzhiyun        interrupts = <&spi_flash_irq>;
75*4882a593Smuzhiyun        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
76*4882a593Smuzhiyun        clock-names = "spi", "sf";
77*4882a593Smuzhiyun        #address-cells = <1>;
78*4882a593Smuzhiyun        #size-cells = <0>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun        flash@0 {
81*4882a593Smuzhiyun          compatible = "jedec,spi-nor";
82*4882a593Smuzhiyun          reg = <0>;
83*4882a593Smuzhiyun        };
84*4882a593Smuzhiyun      };
85*4882a593Smuzhiyun    };
86*4882a593Smuzhiyun
87