1*4882a593Smuzhiyun* SPI (Serial Peripheral Interface) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- cell-index : QE SPI subblock index. 5*4882a593Smuzhiyun 0: QE subblock SPI1 6*4882a593Smuzhiyun 1: QE subblock SPI2 7*4882a593Smuzhiyun- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 8*4882a593Smuzhiyun- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 10*4882a593Smuzhiyun- interrupts : <a b> where a is the interrupt number and b is a 11*4882a593Smuzhiyun field that represents an encoding of the sense and level 12*4882a593Smuzhiyun information for the interrupt. This should be encoded based on 13*4882a593Smuzhiyun the information in section 2) depending on the type of interrupt 14*4882a593Smuzhiyun controller you have. 15*4882a593Smuzhiyun- clock-frequency : input clock frequency to non FSL_SOC cores 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- cs-gpios : specifies the gpio pins to be used for chipselects. 19*4882a593Smuzhiyun The gpios will be referred to as reg = <index> in the SPI child nodes. 20*4882a593Smuzhiyun If unspecified, a single SPI device without a chip select can be used. 21*4882a593Smuzhiyun- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the 22*4882a593Smuzhiyun SPISEL_BOOT signal is used as chip select for a slave device. Use 23*4882a593Smuzhiyun reg = <number of gpios> in the corresponding child node, i.e. 0 if 24*4882a593Smuzhiyun the cs-gpios property is not present. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun spi@4c0 { 28*4882a593Smuzhiyun cell-index = <0>; 29*4882a593Smuzhiyun compatible = "fsl,spi"; 30*4882a593Smuzhiyun reg = <4c0 40>; 31*4882a593Smuzhiyun interrupts = <82 0>; 32*4882a593Smuzhiyun interrupt-parent = <700>; 33*4882a593Smuzhiyun mode = "cpu"; 34*4882a593Smuzhiyun cs-gpios = <&gpio 18 1 // device reg=<0> 35*4882a593Smuzhiyun &gpio 19 1>; // device reg=<1> 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun* eSPI (Enhanced Serial Peripheral Interface) 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunRequired properties: 42*4882a593Smuzhiyun- compatible : should be "fsl,mpc8536-espi". 43*4882a593Smuzhiyun- reg : Offset and length of the register set for the device. 44*4882a593Smuzhiyun- interrupts : should contain eSPI interrupt, the device has one interrupt. 45*4882a593Smuzhiyun- fsl,espi-num-chipselects : the number of the chipselect signals. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunOptional properties: 48*4882a593Smuzhiyun- fsl,csbef: chip select assertion time in bits before frame starts 49*4882a593Smuzhiyun- fsl,csaft: chip select negation time in bits after frame ends 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunExample: 52*4882a593Smuzhiyun spi@110000 { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun compatible = "fsl,mpc8536-espi"; 56*4882a593Smuzhiyun reg = <0x110000 0x1000>; 57*4882a593Smuzhiyun interrupts = <53 0x2>; 58*4882a593Smuzhiyun interrupt-parent = <&mpic>; 59*4882a593Smuzhiyun fsl,espi-num-chipselects = <4>; 60*4882a593Smuzhiyun fsl,csbef = <1>; 61*4882a593Smuzhiyun fsl,csaft = <1>; 62*4882a593Smuzhiyun }; 63