1*4882a593SmuzhiyunBroadcom BCM2835 auxiliar SPI1/2 controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe BCM2835 contains two forms of SPI master controller, one known simply as 4*4882a593SmuzhiyunSPI0, and the other known as the "Universal SPI Master"; part of the 5*4882a593Smuzhiyunauxiliary block. This binding applies to the SPI1/2 controller. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Should be "brcm,bcm2835-aux-spi". 9*4882a593Smuzhiyun- reg: Should contain register location and length for the spi block 10*4882a593Smuzhiyun- interrupts: Should contain shared interrupt of the aux block 11*4882a593Smuzhiyun- clocks: The clock feeding the SPI controller - needs to 12*4882a593Smuzhiyun point to the auxiliar clock driver of the bcm2835, 13*4882a593Smuzhiyun as this clock will enable the output gate for the specific 14*4882a593Smuzhiyun clock. 15*4882a593Smuzhiyun- cs-gpios: the cs-gpios (native cs is NOT supported) 16*4882a593Smuzhiyun see also spi-bus.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunspi1@7e215080 { 21*4882a593Smuzhiyun compatible = "brcm,bcm2835-aux-spi"; 22*4882a593Smuzhiyun reg = <0x7e215080 0x40>; 23*4882a593Smuzhiyun interrupts = <1 29>; 24*4882a593Smuzhiyun clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunspi2@7e2150c0 { 31*4882a593Smuzhiyun compatible = "brcm,bcm2835-aux-spi"; 32*4882a593Smuzhiyun reg = <0x7e2150c0 0x40>; 33*4882a593Smuzhiyun interrupts = <1 29>; 34*4882a593Smuzhiyun clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>; 35*4882a593Smuzhiyun #address-cells = <1>; 36*4882a593Smuzhiyun #size-cells = <0>; 37*4882a593Smuzhiyun cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>; 38*4882a593Smuzhiyun}; 39