1*4882a593Smuzhiyun* Atmel Quad Serial Peripheral Interface (QSPI) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be one of the following: 5*4882a593Smuzhiyun - "atmel,sama5d2-qspi" 6*4882a593Smuzhiyun - "microchip,sam9x60-qspi" 7*4882a593Smuzhiyun- reg: Should contain the locations and lengths of the base registers 8*4882a593Smuzhiyun and the mapped memory. 9*4882a593Smuzhiyun- reg-names: Should contain the resource reg names: 10*4882a593Smuzhiyun - qspi_base: configuration register address space 11*4882a593Smuzhiyun - qspi_mmap: memory mapped address space 12*4882a593Smuzhiyun- interrupts: Should contain the interrupt for the device. 13*4882a593Smuzhiyun- clocks: Should reference the peripheral clock and the QSPI system 14*4882a593Smuzhiyun clock if available. 15*4882a593Smuzhiyun- clock-names: Should contain "pclk" for the peripheral clock and "qspick" 16*4882a593Smuzhiyun for the system clock when available. 17*4882a593Smuzhiyun- #address-cells: Should be <1>. 18*4882a593Smuzhiyun- #size-cells: Should be <0>. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunspi@f0020000 { 23*4882a593Smuzhiyun compatible = "atmel,sama5d2-qspi"; 24*4882a593Smuzhiyun reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; 25*4882a593Smuzhiyun reg-names = "qspi_base", "qspi_mmap"; 26*4882a593Smuzhiyun interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 27*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 28*4882a593Smuzhiyun clock-names = "pclk"; 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spi0_default>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun m25p80@0 { 35*4882a593Smuzhiyun ... 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38