1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A10 SPI Controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunallOf: 10*4882a593Smuzhiyun - $ref: "spi-controller.yaml" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunmaintainers: 13*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 14*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun "#address-cells": true 18*4882a593Smuzhiyun "#size-cells": true 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: allwinner,sun4i-a10-spi 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun items: 31*4882a593Smuzhiyun - description: Bus Clock 32*4882a593Smuzhiyun - description: Module Clock 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-names: 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun - const: ahb 37*4882a593Smuzhiyun - const: mod 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun dmas: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - description: RX DMA Channel 42*4882a593Smuzhiyun - description: TX DMA Channel 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun dma-names: 45*4882a593Smuzhiyun items: 46*4882a593Smuzhiyun - const: rx 47*4882a593Smuzhiyun - const: tx 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun num-cs: true 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunpatternProperties: 52*4882a593Smuzhiyun "^.*@[0-9a-f]+": 53*4882a593Smuzhiyun type: object 54*4882a593Smuzhiyun properties: 55*4882a593Smuzhiyun reg: 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun minimum: 0 58*4882a593Smuzhiyun maximum: 4 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun spi-rx-bus-width: 61*4882a593Smuzhiyun const: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun spi-tx-bus-width: 64*4882a593Smuzhiyun const: 1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunrequired: 67*4882a593Smuzhiyun - compatible 68*4882a593Smuzhiyun - reg 69*4882a593Smuzhiyun - interrupts 70*4882a593Smuzhiyun - clocks 71*4882a593Smuzhiyun - clock-names 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunadditionalProperties: false 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunexamples: 76*4882a593Smuzhiyun - | 77*4882a593Smuzhiyun spi1: spi@1c06000 { 78*4882a593Smuzhiyun compatible = "allwinner,sun4i-a10-spi"; 79*4882a593Smuzhiyun reg = <0x01c06000 0x1000>; 80*4882a593Smuzhiyun interrupts = <11>; 81*4882a593Smuzhiyun clocks = <&ahb_gates 21>, <&spi1_clk>; 82*4882a593Smuzhiyun clock-names = "ahb", "mod"; 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun... 88