1*4882a593SmuzhiyunZTE ZX296702 SPDIF controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Must be "zte,zx296702-spdif" 5*4882a593Smuzhiyun - reg : Must contain SPDIF core's registers location and length 6*4882a593Smuzhiyun - clocks : Pairs of phandle and specifier referencing the controller's clocks. 7*4882a593Smuzhiyun - clock-names: "tx" for the clock to the SPDIF interface. 8*4882a593Smuzhiyun - dmas: Pairs of phandle and specifier for the DMA channel that is used by 9*4882a593Smuzhiyun the core. The core expects one dma channel for transmit. 10*4882a593Smuzhiyun - dma-names : Must be "tx" 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunFor more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties 13*4882a593Smuzhiyunplease check: 14*4882a593Smuzhiyun * resource-names.txt 15*4882a593Smuzhiyun * clock/clock-bindings.txt 16*4882a593Smuzhiyun * dma/dma.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun spdif0: spdif0@b004000 { 20*4882a593Smuzhiyun compatible = "zte,zx296702-spdif"; 21*4882a593Smuzhiyun reg = <0x0b004000 0x1000>; 22*4882a593Smuzhiyun clocks = <&lsp0clk ZX296702_SPDIF0_DIV>; 23*4882a593Smuzhiyun clock-names = "tx"; 24*4882a593Smuzhiyun interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 25*4882a593Smuzhiyun dmas = <&dma 4>; 26*4882a593Smuzhiyun dma-names = "tx"; 27*4882a593Smuzhiyun }; 28