1*4882a593SmuzhiyunZTE TDM DAI driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : should be one of the following. 6*4882a593Smuzhiyun * zte,zx296718-tdm 7*4882a593Smuzhiyun- reg : physical base address of the controller and length of memory mapped 8*4882a593Smuzhiyun region. 9*4882a593Smuzhiyun- clocks : Pairs of phandle and specifier referencing the controller's clocks. 10*4882a593Smuzhiyun- clock-names: "wclk" for the wclk. 11*4882a593Smuzhiyun "pclk" for the pclk. 12*4882a593Smuzhiyun-#clock-cells: should be 1. 13*4882a593Smuzhiyun- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling 14*4882a593Smuzhiyun the dma. includes: 15*4882a593Smuzhiyun phandle of sysctrl. 16*4882a593Smuzhiyun register offset in sysctrl for control dma. 17*4882a593Smuzhiyun mask of the register that be written to sysctrl. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun tdm: tdm@1487000 { 22*4882a593Smuzhiyun compatible = "zte,zx296718-tdm"; 23*4882a593Smuzhiyun reg = <0x01487000 0x1000>; 24*4882a593Smuzhiyun clocks = <&audiocrm AUDIO_TDM_WCLK>, <&audiocrm AUDIO_TDM_PCLK>; 25*4882a593Smuzhiyun clock-names = "wclk", "pclk"; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun pinctrl-names = "default"; 28*4882a593Smuzhiyun pinctrl-0 = <&tdm_global_pin>; 29*4882a593Smuzhiyun zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>; 30*4882a593Smuzhiyun }; 31