1*4882a593SmuzhiyunDevice-Tree bindings for Xilinx I2S PL block 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe IP supports I2S based playback/capture audio 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired property: 6*4882a593Smuzhiyun - compatible: "xlnx,i2s-transmitter-1.0" for playback and 7*4882a593Smuzhiyun "xlnx,i2s-receiver-1.0" for capture 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired property common to both I2S playback and capture: 10*4882a593Smuzhiyun - reg: Base address and size of the IP core instance. 11*4882a593Smuzhiyun - xlnx,dwidth: sample data width. Can be any of 16, 24. 12*4882a593Smuzhiyun - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. 13*4882a593Smuzhiyun supported channels = 2 * xlnx,num-channels 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun i2s_receiver@a0080000 { 18*4882a593Smuzhiyun compatible = "xlnx,i2s-receiver-1.0"; 19*4882a593Smuzhiyun reg = <0x0 0xa0080000 0x0 0x10000>; 20*4882a593Smuzhiyun xlnx,dwidth = <0x18>; 21*4882a593Smuzhiyun xlnx,num-channels = <1>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun i2s_transmitter@a0090000 { 24*4882a593Smuzhiyun compatible = "xlnx,i2s-transmitter-1.0"; 25*4882a593Smuzhiyun reg = <0x0 0xa0090000 0x0 0x10000>; 26*4882a593Smuzhiyun xlnx,dwidth = <0x18>; 27*4882a593Smuzhiyun xlnx,num-channels = <1>; 28*4882a593Smuzhiyun }; 29