1*4882a593SmuzhiyunDevice-Tree bindings for Xilinx PL audio formatter 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe IP core supports DMA, data formatting(AES<->PCM conversion) 4*4882a593Smuzhiyunof audio samples. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun - compatible: "xlnx,audio-formatter-1.0" 8*4882a593Smuzhiyun - interrupt-names: Names specified to list of interrupts in same 9*4882a593Smuzhiyun order mentioned under "interrupts". 10*4882a593Smuzhiyun List of supported interrupt names are: 11*4882a593Smuzhiyun "irq_mm2s" : interrupt from MM2S block 12*4882a593Smuzhiyun "irq_s2mm" : interrupt from S2MM block 13*4882a593Smuzhiyun - interrupts-parent: Phandle for interrupt controller. 14*4882a593Smuzhiyun - interrupts: List of Interrupt numbers. 15*4882a593Smuzhiyun - reg: Base address and size of the IP core instance. 16*4882a593Smuzhiyun - clock-names: List of input clocks. 17*4882a593Smuzhiyun Required elements: "s_axi_lite_aclk", "aud_mclk" 18*4882a593Smuzhiyun - clocks: Input clock specifier. Refer to common clock bindings. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun audio_ss_0_audio_formatter_0: audio_formatter@80010000 { 22*4882a593Smuzhiyun compatible = "xlnx,audio-formatter-1.0"; 23*4882a593Smuzhiyun interrupt-names = "irq_mm2s", "irq_s2mm"; 24*4882a593Smuzhiyun interrupt-parent = <&gic>; 25*4882a593Smuzhiyun interrupts = <0 104 4>, <0 105 4>; 26*4882a593Smuzhiyun reg = <0x0 0x80010000 0x0 0x1000>; 27*4882a593Smuzhiyun clock-names = "s_axi_lite_aclk", "aud_mclk"; 28*4882a593Smuzhiyun clocks = <&clk 71>, <&clk_wiz_1 0>; 29*4882a593Smuzhiyun }; 30