1*4882a593SmuzhiyunDevice-Tree bindings for Xilinx SPDIF IP 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe IP supports playback and capture of SPDIF audio 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun - compatible: "xlnx,spdif-2.0" 7*4882a593Smuzhiyun - clock-names: List of input clocks. 8*4882a593Smuzhiyun Required elements: "s_axi_aclk", "aud_clk_i" 9*4882a593Smuzhiyun - clocks: Input clock specifier. Refer to common clock bindings. 10*4882a593Smuzhiyun - reg: Base address and address length of the IP core instance. 11*4882a593Smuzhiyun - interrupts-parent: Phandle for interrupt controller. 12*4882a593Smuzhiyun - interrupts: List of Interrupt numbers. 13*4882a593Smuzhiyun - xlnx,spdif-mode: 0 :- receiver mode 14*4882a593Smuzhiyun 1 :- transmitter mode 15*4882a593Smuzhiyun - xlnx,aud_clk_i: input audio clock value. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun spdif_0: spdif@80010000 { 19*4882a593Smuzhiyun clock-names = "aud_clk_i", "s_axi_aclk"; 20*4882a593Smuzhiyun clocks = <&misc_clk_0>, <&clk 71>; 21*4882a593Smuzhiyun compatible = "xlnx,spdif-2.0"; 22*4882a593Smuzhiyun interrupt-names = "spdif_interrupt"; 23*4882a593Smuzhiyun interrupt-parent = <&gic>; 24*4882a593Smuzhiyun interrupts = <0 91 4>; 25*4882a593Smuzhiyun reg = <0x0 0x80010000 0x0 0x10000>; 26*4882a593Smuzhiyun xlnx,spdif-mode = <1>; 27*4882a593Smuzhiyun xlnx,aud_clk_i = <49152913>; 28*4882a593Smuzhiyun }; 29