1*4882a593SmuzhiyunWM8962 audio CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis device supports I2C only. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - compatible : "wlf,wm8962" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - reg : the I2C address of the device. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional properties: 12*4882a593Smuzhiyun - spk-mono: This is a boolean property. If present, the SPK_MONO bit 13*4882a593Smuzhiyun of R51 (Class D Control 2) gets set, indicating that the speaker is 14*4882a593Smuzhiyun in mono mode. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - mic-cfg : Default register value for R48 (Additional Control 4). 17*4882a593Smuzhiyun If absent, the default should be the register default. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - gpio-cfg : A list of GPIO configuration register values. The list must 20*4882a593Smuzhiyun be 6 entries long. If absent, no configuration of these registers is 21*4882a593Smuzhiyun performed. And note that only the value within [0x0, 0xffff] is valid. 22*4882a593Smuzhiyun Any other value is regarded as setting the GPIO register by its reset 23*4882a593Smuzhiyun value 0x0. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunwm8962: codec@1a { 28*4882a593Smuzhiyun compatible = "wlf,wm8962"; 29*4882a593Smuzhiyun reg = <0x1a>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio-cfg = < 32*4882a593Smuzhiyun 0x0000 /* 0:Default */ 33*4882a593Smuzhiyun 0x0000 /* 1:Default */ 34*4882a593Smuzhiyun 0x0013 /* 2:FN_DMICCLK */ 35*4882a593Smuzhiyun 0x0000 /* 3:Default */ 36*4882a593Smuzhiyun 0x8014 /* 4:FN_DMICCDAT */ 37*4882a593Smuzhiyun 0x0000 /* 5:Default */ 38*4882a593Smuzhiyun >; 39*4882a593Smuzhiyun}; 40