1*4882a593SmuzhiyunWM8903 audio CODEC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis device supports I2C only. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - compatible : "wlf,wm8903" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - reg : the I2C address of the device. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - gpio-controller : Indicates this device is a GPIO controller. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - #gpio-cells : Should be two. The first cell is the pin number and the 14*4882a593Smuzhiyun second cell is used to specify optional parameters (currently unused). 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun - interrupts : The interrupt line the codec is connected to. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the 21*4882a593Smuzhiyun default is 0. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - micdet-delay : The debounce delay for microphone detection in mS. If 24*4882a593Smuzhiyun absent, the default is 100. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun - gpio-cfg : A list of GPIO configuration register values. The list must 27*4882a593Smuzhiyun be 5 entries long. If absent, no configuration of these registers is 28*4882a593Smuzhiyun performed. If any entry has the value 0xffffffff, that GPIO's 29*4882a593Smuzhiyun configuration will not be modified. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun - AVDD-supply : Analog power supply regulator on the AVDD pin. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun - CPVDD-supply : Charge pump supply regulator on the CPVDD pin. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun - DBVDD-supply : Digital buffer supply regulator for the DBVDD pin. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun - DCVDD-supply : Digital core supply regulator for the DCVDD pin. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunPins on the device (for linking into audio routes): 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun * IN1L 42*4882a593Smuzhiyun * IN1R 43*4882a593Smuzhiyun * IN2L 44*4882a593Smuzhiyun * IN2R 45*4882a593Smuzhiyun * IN3L 46*4882a593Smuzhiyun * IN3R 47*4882a593Smuzhiyun * DMICDAT 48*4882a593Smuzhiyun * HPOUTL 49*4882a593Smuzhiyun * HPOUTR 50*4882a593Smuzhiyun * LINEOUTL 51*4882a593Smuzhiyun * LINEOUTR 52*4882a593Smuzhiyun * LOP 53*4882a593Smuzhiyun * LON 54*4882a593Smuzhiyun * ROP 55*4882a593Smuzhiyun * RON 56*4882a593Smuzhiyun * MICBIAS 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunExample: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunwm8903: codec@1a { 61*4882a593Smuzhiyun compatible = "wlf,wm8903"; 62*4882a593Smuzhiyun reg = <0x1a>; 63*4882a593Smuzhiyun interrupts = < 347 >; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun AVDD-supply = <&fooreg_a>; 66*4882a593Smuzhiyun CPVDD-supply = <&fooreg_b>; 67*4882a593Smuzhiyun DBVDD-supply = <&fooreg_c>; 68*4882a593Smuzhiyun DCVDC-supply = <&fooreg_d>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun gpio-controller; 71*4882a593Smuzhiyun #gpio-cells = <2>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun micdet-cfg = <0>; 74*4882a593Smuzhiyun micdet-delay = <100>; 75*4882a593Smuzhiyun gpio-cfg = < 76*4882a593Smuzhiyun 0x0600 /* DMIC_LR, output */ 77*4882a593Smuzhiyun 0x0680 /* DMIC_DAT, input */ 78*4882a593Smuzhiyun 0x0000 /* GPIO, output, low */ 79*4882a593Smuzhiyun 0x0200 /* Interrupt, output */ 80*4882a593Smuzhiyun 0x01a0 /* BCLK, input, active high */ 81*4882a593Smuzhiyun >; 82*4882a593Smuzhiyun}; 83