1*4882a593Smuzhiyun* SiRF SoC USP module 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "sirf,prima2-usp-pcm" 5*4882a593Smuzhiyun- reg: Base address and size entries: 6*4882a593Smuzhiyun- dmas: List of DMA controller phandle and DMA request line ordered pairs. 7*4882a593Smuzhiyun- dma-names: Identifier string for each DMA request line in the dmas property. 8*4882a593Smuzhiyun These strings correspond 1:1 with the ordered pairs in dmas. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun One of the DMA channels will be responsible for transmission (should be 11*4882a593Smuzhiyun named "tx") and one for reception (should be named "rx"). 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- clocks: USP controller clock source 14*4882a593Smuzhiyun- pinctrl-names: Must contain a "default" entry. 15*4882a593Smuzhiyun- pinctrl-NNN: One property must exist for each entry in pinctrl-names. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyunusp0: usp@b0080000 { 19*4882a593Smuzhiyun compatible = "sirf,prima2-usp-pcm"; 20*4882a593Smuzhiyun reg = <0xb0080000 0x10000>; 21*4882a593Smuzhiyun clocks = <&clks 28>; 22*4882a593Smuzhiyun dmas = <&dmac1 1>, <&dmac1 2>; 23*4882a593Smuzhiyun dma-names = "rx", "tx"; 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&usp0_only_utfs_pins_a>; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28