xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Rockchip RK3308 Internal Codec
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun- compatible: "rockchip,rk3308-codec"
6*4882a593Smuzhiyun- reg: The physical base address of the controller and length of memory
7*4882a593Smuzhiyun  mapped region.
8*4882a593Smuzhiyun- rockchip,grf: The phandle of the syscon node for GRF register.
9*4882a593Smuzhiyun- clocks: A list of phandle + clock-specifer pairs, one for each entry in
10*4882a593Smuzhiyun  clock-names.
11*4882a593Smuzhiyun- clock-names: It should be "acodec".
12*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names.
13*4882a593Smuzhiyun- reset-names : Must include the following entries: "acodec-reset".
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunOptional properties:
16*4882a593Smuzhiyun- rockchip,enable-all-adcs: This is a boolean type property, that shows whether
17*4882a593Smuzhiyun  force enable all of ADCs. The following shows the relationship between grps
18*4882a593Smuzhiyun  and ADC:
19*4882a593Smuzhiyun  * grp 0 -- select ADC1 / ADC2
20*4882a593Smuzhiyun  * grp 1 -- select ADC3 / ADC4
21*4882a593Smuzhiyun  * grp 2 -- select ADC5 / ADC6
22*4882a593Smuzhiyun  * grp 3 -- select ADC7 / ADC8
23*4882a593Smuzhiyun  If the property is not used, the enabled ADC groups refer to needed channels
24*4882a593Smuzhiyun  via configure hw_params.
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun- rockchip,adc-grps-route: This is a variable length array, that shows the
27*4882a593Smuzhiyun  mapping route of ACODEC sdo to I2S sdi. By default, they are one-to-one
28*4882a593Smuzhiyun  mapping:
29*4882a593Smuzhiyun  * sdi_0 <-- sdo_0
30*4882a593Smuzhiyun  * sdi_1 <-- sdo_1
31*4882a593Smuzhiyun  * sdi_2 <-- sdo_2
32*4882a593Smuzhiyun  * sdi_3 <-- sdo_3
33*4882a593Smuzhiyun  If you would like to change the route mapping like this:
34*4882a593Smuzhiyun  * sdi_0 <-- sdo_3
35*4882a593Smuzhiyun  * sdi_1 <-- sdo_0
36*4882a593Smuzhiyun  * sdi_2 <-- sdo_2
37*4882a593Smuzhiyun  * sdi_3 <-- sdo_1
38*4882a593Smuzhiyun  You need to add the property on dts:
39*4882a593Smuzhiyun  - rockchip,adc-grps-route = <3 0 2 1>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun- rockchip,delay-loopback-handle-ms: This property points out that the delay for
42*4882a593Smuzhiyun  handling ADC after enable PAs during loopback.
43*4882a593Smuzhiyun- rockchip,delay-start-play-ms: This property points out the delay ms of start
44*4882a593Smuzhiyun  playback according to different amplifier performance.
45*4882a593Smuzhiyun- rockchip,en-always-grps: This property will keep the needed ADCs enabled
46*4882a593Smuzhiyun  always after enabling once.
47*4882a593Smuzhiyun- rockchip,loopback-grp: It points out the ADC group which is the loopback used.
48*4882a593Smuzhiyun- rockchip,no-deep-low-power: The codec will not enter deep low power mode
49*4882a593Smuzhiyun  during suspend.
50*4882a593Smuzhiyun- rockchip,no-hp-det: If there is no headphone on boards, we don't need to
51*4882a593Smuzhiyun  enable headphone detection.
52*4882a593Smuzhiyun- rockchip,micbias1: Using internal micbias1 supply which are from codec.
53*4882a593Smuzhiyun- rockchip,micbias2: Using internal micbias2 supply which are from codec.
54*4882a593Smuzhiyun- hp-ctl-gpios: The gpio of head phone controller.
55*4882a593Smuzhiyun- pa-drv-gpios: The gpio of poweramplifier controller
56*4882a593Smuzhiyun- rockchip,delay-pa-drv-ms: This property points out that the delay for
57*4882a593Smuzhiyun  power on amplifier
58*4882a593Smuzhiyun- spk-ctl-gpios: The gpio of speak controller.
59*4882a593Smuzhiyun
60*4882a593SmuzhiyunExample for rk3308 internal codec:
61*4882a593Smuzhiyun
62*4882a593Smuzhiyunacodec: acodec@ff560000 {
63*4882a593Smuzhiyun	compatible = "rockchip,rk3308-codec";
64*4882a593Smuzhiyun	reg = <0x0 0xff560000 0x0 0x10000>;
65*4882a593Smuzhiyun	rockchip,grf = <&grf>;
66*4882a593Smuzhiyun	clocks = <&cru PCLK_ACODEC>;
67*4882a593Smuzhiyun	clock-names = "acodec";
68*4882a593Smuzhiyun	resets = <&cru SRST_ACODEC_P>;
69*4882a593Smuzhiyun	reset-names = "acodec-reset";
70*4882a593Smuzhiyun	rockchip,loopback-grp = <0>;
71*4882a593Smuzhiyun	hp-ctl-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
72*4882a593Smuzhiyun	pa-drv-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
73*4882a593Smuzhiyun	spk-ctl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
74*4882a593Smuzhiyun	status = "okay";
75*4882a593Smuzhiyun};
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